公开(公告)号：US07504900B2

公开(公告)日：2009-03-17

申请号：US11694624

申请日：2007-03-30

申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC分类号： G06F1/04 ,  H03B5/00 ,  H03B5/12 ,  H03B5/24 ,  H03B5/36

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

摘要翻译： 集成电路封装包括处理核心和内部振荡器。 处理核心通过一组指令来执行预定义的过程。 内部振荡器为集成电路封装提供系统时钟。 内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

公开(公告)号：US20080155289A1

公开(公告)日：2008-06-26

申请号：US12046321

申请日：2008-03-11

申请人： KENNETH W. FERNALD ,  DONALD E. ALFANO

发明人： KENNETH W. FERNALD ,  DONALD E. ALFANO

IPC分类号： G06F1/32 ,  G06F1/14

CPC分类号： G06F1/3203

摘要： A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.

摘要翻译： 公开了具有独立实时时钟（RTC）的微控制器单元（MCU）。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。 主时钟电路为处理电路提供定时。 电源控制电路控制处理电路和主时钟电路的电源，以控制其工作在至少全功率模式下工作，从供电电压输入和低功耗模式绘制小于全功率模式 功率电平从电源电压输入。 还提供独立的RTC电路，独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。 由RTC时钟电路计时钟的定时器可操作以增加存储的时间值以便从其输出，RTC时钟电路具有确定的时基。 输入/输出（I / O）设备提供处理电路对定时器输出的结果的访问。 电源管理电路管理独立RTC电路的电源，使得RTC时钟电路，定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。

公开(公告)号：US07362554B2

公开(公告)日：2008-04-22

申请号：US10431942

申请日：2003-05-08

申请人： James Dub Austin ,  Kenneth W. Fernald

发明人： James Dub Austin ,  Kenneth W. Fernald

IPC分类号： H02H3/22

CPC分类号： H01L27/0285

摘要： Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.

摘要翻译： 使用输出驱动器的静电放电（ESD）钳位。 一种用于输出驱动器的静电放电（ESD）保护装置，其具有连接在电源端子和地之间的p沟道晶体管和n型晶体管对，用于驱动输入/输出衬垫。 提供ESD事件检测器，用于检测焊盘上的ESD事件。 驱动电路响应于接收到逻辑控制信号而驱动n沟道和p沟道驱动晶体管，以从供电端驱动焊盘或将焊盘吸收到地。 提供ESD保护逻辑电路以在ESD事件检测器检测到ESD事件时使p沟道晶体管和n沟道晶体管导通，ESD保护电路设置在驱动电路的前方，使得ESD保护逻辑电路独立运行 的驱动电路的状态。

公开(公告)号：US07343504B2

公开(公告)日：2008-03-11

申请号：US10881793

申请日：2004-06-30

申请人： Kenneth W. Fernald ,  Donald E. Alfano

发明人： Kenneth W. Fernald ,  Donald E. Alfano

IPC分类号： G06F1/26

CPC分类号： G06F1/3203

摘要： A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.

摘要翻译： 公开了具有独立实时时钟（RTC）的微控制器单元（MCU）。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。 主时钟电路为处理电路提供定时。 电源控制电路控制处理电路和主时钟电路的电源，以控制其工作在至少全功率模式下工作，从供电电压输入和低功耗模式绘制小于全功率模式 功率电平从电源电压输入。 还提供独立的RTC电路，独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。 由RTC时钟电路计时钟的定时器可操作以增加存储的时间值以便从其输出，RTC时钟电路具有确定的时基。 输入/输出（I / O）设备提供处理电路对定时器输出的结果的访问。 电源管理电路管理独立RTC电路的电源，使得RTC时钟电路，定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。

公开(公告)号：US07303844B2

公开(公告)日：2007-12-04

申请号：US10816573

申请日：2004-03-31

申请人： John Ellis

发明人： John Ellis

IPC分类号： G03F1/00

CPC分类号： G03F1/38

摘要： Marking system for a semiconductor wafer to identify problems in mask layers. A method for forming a mask which includes the step of first creating at least one drawing layer that defines changes to the structures to be formed on the surface of a semiconductor substrate at one step in the processing thereof, which step involves the use of a mask. The at least one drawing layer will define a pattern region that will either result in removal of the material from the semiconductor substrate in the defined pattern region, or removal of matter from the semiconductor substrate around the defined pattern region. An indicator area is created in the at least one drawing layer, the indicator area having an indicator region disposed therein that will result in removal of material from around the indicator region regardless of whether the mask is a dark tone mask or a clear tone mask, the indicator region appearing in the negative if the mask is a dark tone mask. A mask is then created from the at least one drawing layer as either a dark tone mask having a transparent region corresponding to the defined pattern region for exposing the underlying substrate if the defined pattern region is associated with a process that results in material being removed from around the defined pattern region, or as a clear tone mask having an occluding region corresponding to the defined pattern region if the defined pattern region is associated with a process that results in material being removed from the defined pattern region.

摘要翻译： 用于半导体晶片的标记系统以识别掩模层中的问题。 一种形成掩模的方法，其包括以下步骤：首先在其处理中以一步形成至少一个绘制层，该拉伸层限定在半导体衬底的表面上形成的结构的变化，该步骤包括使用掩模 。 至少一个拉伸层将限定将导致在限定的图案区域中从半导体衬底去除材料的图案区域，或者在限定的图案区域周围从半导体衬底去除物质。 在所述至少一个绘图层中产生指示区域，所述指示器区域具有设置在其中的指示器区域，其将导致从所述指示器区域周围移除材料，而不管掩模是暗色掩码还是清晰色调掩模， 如果掩模是暗色调掩模，则指示符区域出现在负数。 然后从至少一个绘图层创建掩模作为具有对应于所定义的图案区域的透明区域的暗色调掩模，用于暴露下面的衬底，如果限定的图案区域与导致材料被从 如果限定的图案区域与导致材料从限定的图案区域移除的过程相关联，则作为具有对应于限定图案区域的闭塞区域的清晰色调掩模。

公开(公告)号：US07250825B2

公开(公告)日：2007-07-31

申请号：US10865110

申请日：2004-06-10

申请人： Brent Wilson ,  Paul Highley ,  Kenneth W. Fernald

发明人： Brent Wilson ,  Paul Highley ,  Kenneth W. Fernald

IPC分类号： G01R23/10 ,  H03I1/00

CPC分类号： H03L7/08 ,  H03L1/02

摘要： Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

摘要翻译： 用于在基于处理器的系统中校准低频振荡器的方法和装置。 一种用于校准片上非精密振荡器的方法。 提供具有在可接受的工作公差内的已知操作频率的片上精密振荡器。 片上精密振荡器用作时基，然后根据时基测量片上振荡器的周期。 然后确定片上非精密振荡器的测量频率与片上非精密振荡器的期望工作频率之间的差异。 在确定差异之后，调整片上非精密振荡器的频率以使确定的差最小化。

公开(公告)号：US07119526B2

公开(公告)日：2006-10-10

申请号：US10944640

申请日：2004-09-17

申请人： Kenneth W. Fernald

发明人： Kenneth W. Fernald

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

摘要翻译： 一种电压监视器，具有由待监视电压驱动的带隙基准电路。 带隙参考电路产生电压和第二电压，每个电压和待监控的电压各自变化。 这些电压的大小由开环比较器进行比较，以提供高速输出状态。 如果电源电压降至低于规定阈值的幅度，则电压监视器的输出可用于监视电源电压并产生一个复位信号给处理器。

公开(公告)号：US07071733B2

公开(公告)日：2006-07-04

申请号：US10847632

申请日：2004-05-17

申请人： Kenneth W. Fernald ,  Donald E. Alfano

发明人： Kenneth W. Fernald ,  Donald E. Alfano

IPC分类号： H03K19/177

CPC分类号： H04Q3/52 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/1325

摘要： A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

摘要翻译： 形成交叉条形码解码器（310）的路由信元的矩阵。 基于微处理器的控制，信号三元组通过交叉条形码解码器（310）耦合。 寄存器（50）向跨栏解码器（310）提供控制信号，以通过交叉条形码解码器（310）的单元激活或去激活三联信号的路由。 路由单元被排列成列和行的矩阵。 每行单元格与公共数据信号输入相关联，矩阵的每一列与一个公共I / O引脚相关联。 这些单元由微处理器单独使能，以便任何数据信号可以耦合到任何I / O引脚。 除了通过单元格路由数据信号之外，其他信号也通过单元进行路由。

公开(公告)号：US06917658B2

公开(公告)日：2005-07-12

申请号：US10244728

申请日：2002-09-16

申请人： Kenneth W. Fernald

发明人： Kenneth W. Fernald

IPC分类号： H03K3/0231 ,  H03L7/08 ,  H03L7/085 ,  H04L7/033 ,  H04L7/00

CPC分类号： H04L7/0331 ,  H03K3/0231 ,  H03L7/08 ,  H03L7/085 ,  H03L2207/50

摘要： Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data between the bursts of data. A receive clock is provided that operates within a reference frequency range. The time between data transitions in the received data is then measuring relative to the receive clock. A determination is then made if the measured time is substantially an integral of the receive clock. If not a substantial integral of the receive clock, the frequency of the receive clock is adjusted to compensate for the difference.

摘要翻译： 用于突发通信的时钟恢复方法。 公开了一种用于从接收到的数据流中恢复时钟的方法，该数据流包括数据脉冲串与数据脉冲之间基本上没有数据的区域。 提供在参考频率范围内工作的接收时钟。 接收数据中的数据转换之间的时间就是相对于接收时钟进行测量。 然后，如果测量的时间基本上是接收时钟的积分，则进行确定。 如果不是接收时钟的实质积分，则调整接收时钟的频率以补偿差分。

公开(公告)号：US06891487B2

公开(公告)日：2005-05-10

申请号：US10752913

申请日：2004-01-07

申请人： Ka Y. Leung ,  Douglas R. Holberg ,  Kafai Leung

发明人： Ka Y. Leung ,  Douglas R. Holberg ,  Kafai Leung

IPC分类号： G06F13/28 ,  H01C10/16 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/38 ,  H03M1/46 ,  H03M1/66 ,  H03M1/78

CPC分类号： H03M1/1057 ,  H03M1/468

摘要： Capacitor calibration in SAR converter. A method for calibrating a switched capacitor array in a SAR data converter is disclosed, which array includes a plurality of primary capacitors having a common node plate interfaced to a common node and a switched plate interfaced to a switch that is operable to be switched between first and second reference voltages. A comparator having an input connected to the common node and a reference input connected to a comparator reference node receives a comparator reference voltage. In a first calibration step for calibrating one of the primary capacitors, a reference capacitor is provided and then, the switched plate of the select primary capacitor is connected to the first reference voltage, the switched plate of the other capacitors and the reference capacitor are connected to the second reference voltage, and the common node and the comparator reference node are driven with a driver to dispose a first voltage thereon. In a second calibration step, the common node is allowed to float, the switched plate of the select primary capacitor is connected to the second reference voltage, the switched plate of the reference capacitor is connected to the first reference voltage, and the voltage on the common node is compared to the first voltage on the comparator reference node. A determination is then made as to whether the voltage on the common node is greater than the first voltage. A plurality of trim capacitors are provided and, if in the second calibration step, the voltage on the common node was determined to be greater than the first voltage, then one of the trim capacitors is disposed in parallel with the select one of the primary capacitors and then the first and second calibrating steps are repeated.

摘要翻译： SAR转换器中的电容校准。 公开了一种用于校准SAR数据转换器中的开关电容器阵列的方法，该阵列包括具有与公共节点接口的公共节点板的多个初级电容器和与开关接口的开关板，该开关板可操作以在第一 和第二参考电压。 具有连接到公共节点的输入和连接到比较器参考节点的参考输入的比较器接收比较器参考电压。 在用于校准主电容器之一的第一校准步骤中，提供参考电容器，然后，选择一次电容器的开关板连接到第一参考电压，另一电容器的开关板和参考电容器连接 到第二参考电压，并且公共节点和比较器参考节点由驱动器驱动以在其上设置第一电压。 在第二校准步骤中，允许公共节点浮动，选择主电容器的开关板连接到第二参考电压，参考电容器的开关板连接到第一参考电压，并且在 公共节点与比较器参考节点上的第一个电压进行比较。 然后确定公共节点上的电压是否大于第一电压。 提供多个修整电容器，如果在第二校准步骤中，将公共节点上的电压确定为大于第一电压，则将一个修整电容器与主电容器中的选择一个平行设置 然后重复第一和第二校准步骤。