公开(公告)号：US07157794B2

公开(公告)日：2007-01-02

申请号：US10289384

申请日：2002-11-07

Applicant: Hiroyuki Mori

Inventor： Hiroyuki Mori

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/10 ,  H01L2223/6688 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract translation: 半导体器件包括具有主表面的半导体衬底，主表面包括形成有高频电路元件的第一区域和位于第一区域周围的第二区域，并形成有低频电路元件。 半导体器件还包括覆盖主表面的密封树脂; 多个第一外部端子，其形成在第二区域的上方并与高频电路元件电连接，第一外部端子从密封树脂的表面突出。 半导体器件还包括多个第二外部端子，其形成在第二区域上方并且与低频电路元件电连接，第二外部端子从密封树脂的表面突出。

公开(公告)号：US07129587B2

公开(公告)日：2006-10-31

申请号：US10690627

申请日：2003-10-23

Applicant: Takaaki Sasaki

Inventor： Takaaki Sasaki

IPC: H01L23/48

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.

Abstract translation: 半导体封装包括用于在其上安装和固定半导体芯片的基板和连接图案。 衬底上设置有形成在其中的细长开口。 半导体芯片被固定，其表面安装在基板上，并且其电极在细长的开口内对准。 半导体芯片的电极通过导线通过细长开口电连接到连接图案。 细长的开口和电线用树脂密封。

公开(公告)号：US07114113B2

公开(公告)日：2006-09-26

申请号：US10647378

申请日：2003-08-26

Applicant: Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

Inventor： Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

IPC: G06F11/00

CPC classification number: G01R31/31725 ,  G01R31/31723 ,  G01R31/3187 ,  G01R31/31921 ,  G01R31/31926

Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

Abstract translation: 测试电路包括输入电路，用于输入数据以选择相对于要测试的电路的测试模式，并输出与第一时钟同步的测试模式的选择结果;模式产生电路，用于响应于所选择的结果 测试模式，与第二时钟同步地产生测试模式，并将测试模式输出到要测试的电路;以及比较器电路，用于与第二时钟同步地输入要测试的电路的测试结果;以及比较符合/ 测试结果与提供给待测电路的测试模式之间不一致。 测试电路还包括输出电路，用于保持比较电路的比较结果，并与第一时钟同步地输出比较结果。

公开(公告)号：US07111032B2

公开(公告)日：2006-09-19

申请号：US10235541

申请日：2002-09-06

Applicant: Kimito Horie

Inventor： Kimito Horie

IPC: G06F7/72

CPC classification number: G06F7/724 ,  G06F7/722 ,  G06F7/725

Abstract: A residue computing device on a Galois Field, for calculating a residue of a product of a multiplier factor and a multiplicand under a modulo, includes a gate for allowing the multiplier factor to pass therethrough when a leading bit of the multiplicand is 1, an adder for adding a temporary residue and a value obtained by the passage, a gate for allowing the modulo to pass therethrough when a leading bit of a summed value of the adder is 1, and a subtractor for subtracting the modulo from the summed value of the adder when the leading bit of the summed value is 1, wherein a process for setting a value obtained by shifting a subtracted value of the subtractor by one bit, as the temporary residue on the basis of the next clock is repeatedly performed for each clock to thereby calculate the residue.

Abstract translation: Galois Field上的残差计算装置，用于计算乘法系数和被乘数乘积的乘积的残差，该乘法器在模数下包括一个门，用于当被乘数的前导位为1时允许乘数因子通过，一个加法器 用于在加法器的相加值的前导位为1时添加临时残差和通过获得的值，用于允许模数通过的门，以及用于从加法器的和值中减去模的减法器 当相加值的前导位为1时，其中，针对每个时钟重复执行用于将通过将减法器的减法值移位1比特而获得的值作为基于下一个时钟的临时余数的处理，从而 计算残留物。

公开(公告)号：US07095269B2

公开(公告)日：2006-08-22

申请号：US11187837

申请日：2005-07-25

Applicant: Hitoshi Yamada

Inventor： Hitoshi Yamada

IPC: G05F1/575 ,  G05F1/46

CPC classification number: G05F3/205

Abstract: When the substrate bias voltage Vbb lowers by the pumping operation of the charge pump circuit, a drain-to-source resistance of the N-transistor becomes high. When a first power supply voltage Vcc is set at high value, a drain-to-source current of the N-transistor increases (I+ΔI1), however the drain-to-source current decreases (I+ΔI1−ΔI2) by the increase of the drain-to-source current owing to the substrate bias effect so that the increase of the potential of the node N34 caused by the increase of the first power supply voltage VCC is restrained. As a result, a reference level of the substrate bias voltage Vbb does not largely lower than the reference level of the substrate bias voltage. Vbb when the first power supply voltage VCC is in a standard level.

Abstract translation: 当通过电荷泵电路的泵浦操作使衬底偏置电压Vbb降低时，N晶体管的漏极 - 源极电阻变高。 当第一电源电压Vcc被设置为高值时，N晶体管的漏极 - 源极电流增加（I +ΔI1），然而漏极 - 源极电流减小（I +ΔI1 -DeltaI 2 ），由于衬底偏置效应引起的漏极 - 源极电流的增加，从而抑制了由第一电源电压VCC的增加引起的节点N 34的电位的增加。 结果，衬底偏置电压Vbb的参考电平不会大大低于衬底偏置电压的参考电平。 当第一电源电压VCC处于标准电平时，Vbb。

公开(公告)号：US07093063B2

公开(公告)日：2006-08-15

申请号：US10665617

申请日：2003-09-22

Applicant: Yoshihiro Shona

Inventor： Yoshihiro Shona

IPC: G06F12/02

CPC classification number: G11C16/105 ,  G11C16/102 ,  G11C16/16

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract translation: 数据存储装置包括闪速存储器和控制闪速存储器中的数据重写的控制单元。 闪速存储器被划分为扇区，每个扇区在时间T中都是完全可擦除的。在重写操作期间，多个扇区同时擦除一个小于T的时间U，并且新数据被写入经过多次擦除的扇区 现在已经完全抹去了。 新数据通常代替在多个重写操作期间存储在继续被擦除的扇区中的数据。 由于擦除过程持续时间U而不是时间T，所以每次重写操作的持续时间都减少了。

公开(公告)号：US07091831B2

公开(公告)日：2006-08-15

申请号：US10898930

申请日：2004-07-27

Applicant: Ralph E. Crenshaw ,  David W. Grimes ,  L. Peter Larson ,  Andrew Pozsgay

Inventor： Ralph E. Crenshaw ,  David W. Grimes ,  L. Peter Larson ,  Andrew Pozsgay

IPC: G08B11/01

CPC classification number: H04B3/56 ,  H04B3/542 ,  H04B2203/5433 ,  H04B2203/5466 ,  H04B2203/5483

Abstract: A method and apparatus for modifying a power distribution network in a building in order to provide data communication by using a Power Line Carrier (PLC) signal to an approximate electrical central location point of a power distribution system remote from the data entry point of the building. A passive coupler device is attached to a centrally located service panel. The passive coupler receives the Power Line Carrier (PLC) signal from the remote entry point in the building and conditions the signal for entry at the service panel onto each phase of the power distribution network.

Abstract translation: 一种用于修改建筑物中的配电网络的方法和装置，以便通过使用电力线载波（PLC）信号到远离建筑物的数据入口点的配电系统的近似电气中心位置点来提供数据通信 。 无源耦合器装置连接到位于中心的服务面板。 无源耦合器从建筑物的远程入口处接收电力线载波（PLC）信号，并将在服务面板输入的信号调节到配电网络的每个阶段。

公开(公告)号：US07072206B2

公开(公告)日：2006-07-04

申请号：US11087827

申请日：2005-03-24

Applicant: Kenichiro Sugio

Inventor： Kenichiro Sugio

IPC: G11C11/00

CPC classification number: G11C7/12

Abstract: A semiconductor integrated device includes a memory cell holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell has a cutoff circuit that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.

Abstract translation: 半导体集成器件包括存储单元保持位信息; 连接到存储单元的一对位线，通过该位线信息以预定的周期被输入和输出; 以及输出部分，其通过该对和另一位线的一个位线锁存来自存储器单元的输出，并且作为从存储器单元读取的结果输出从一个位线获取的位信息，并且预充电 在访问存储器单元之前的该对位线。 存储单元具有切断电路，当读出保存在存储单元中的位信息时，切断另一位线以保持由预充电产生的电压。

公开(公告)号：US07160812B2

公开(公告)日：2007-01-09

申请号：US10361823

申请日：2003-02-11

Applicant: Hideshi Hamada

Inventor： Hideshi Hamada

IPC: H01L21/302 ,  H01L21/3065 ,  C25F3/30

CPC classification number: H01L21/67069 ,  H01J37/32724 ,  H01J37/32862

Abstract: A method for preventing the deterioration of an electrode caused by the build up of deposits in openings of the electrode. Gas is supplied to each of the openings in order to prevent deposits from adhering to the openings before or after the etching treatment.

Abstract translation: 一种用于防止由电极开口中的沉积物积聚引起的电极劣化的方法。 为了防止在蚀刻处理之前或之后的沉积物附着在开口上，向每个开口供给气体。

公开(公告)号：US07151974B2

公开(公告)日：2006-12-19

申请号：US11061813

申请日：2005-02-22

Applicant: Shunji Hayashi

Inventor： Shunji Hayashi

IPC: G06F19/00

CPC classification number: G06Q10/10 ,  G05B19/41875 ,  G05B2219/31477 ,  G05B2219/32221 ,  Y02P90/14 ,  Y02P90/22

Abstract: In a method of controlling a manufacturing process, operating conditions of plural process steps are monitored during the manufacturing process. A degree of risk is calculated for each of a malfunction operating condition step and subsequent steps. The degree of risk is classified into plural levels and is determined in accordance with a risk point on the basis of the minimum WIP, actual WIP, target WIP, and a weighting factor. A priority of the manufacturing process needing recovery is determined in response to the degree of risk, and an operating condition of the manufacturing process is controlled in response to the priority determination.

Abstract translation: 在制造过程的控制方法中，在制造过程中监视多个工序的操作条件。 针对每个故障运行条件步骤和后续步骤计算风险程度。 风险程度分为多个等级，并根据最小WIP，实际WIP，目标WIP和权重因子根据风险点确定。 响应于风险程度确定需要恢复的制造过程的优先级，并且响应于优先级确定来控制制造过程的操作条件。