公开(公告)号：US07898449B2

公开(公告)日：2011-03-01

申请号：US12562664

申请日：2009-09-18

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20090146854A1

公开(公告)日：2009-06-11

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/12

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

申请人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12 ,  H03F3/45

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US07612700B2

公开(公告)日：2009-11-03

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US07321245B2

公开(公告)日：2008-01-22

申请号：US10808575

申请日：2004-03-25

申请人： Kuniyuki Tani ,  Atsushi Wada

发明人： Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03K3/00

CPC分类号： G11C5/145

摘要： A first bias voltage generating circuit which applies a bias voltage to an amplifier circuit of an AD converter has a driving unit and a control unit. The driving unit includes a first bias circuit and a second bias circuit as a plurality of bias circuits which are connected in parallel and have different current driving capabilities. The first bias circuit and the second bias circuit each include a CMOS transistor which is connected directly between a power supply potential and a ground potential, and a switching element which interrupts a feedthrough current. The drains of the CMOS transistors output the bias voltage. The control unit turns on both or either one of the first bias circuit and the second bias circuit, thereby controlling the current driving capability of the entire driving unit.

摘要翻译： 向AD转换器的放大电路施加偏置电压的第一偏置电压产生电路具有驱动单元和控制单元。 驱动单元包括第一偏置电路和第二偏置电路作为并联连接并具有不同电流驱动能力的多个偏置电路。 第一偏置电路和第二偏置电路各自包括直接连接在电源电位和接地电位之间的CMOS晶体管，以及中断馈通电流的开关元件。 CMOS晶体管的漏极输出偏置电压。 控制单元接通第一偏置电路和第二偏置电路中的任一个或任一个，从而控制整个驱动单元的电流驱动能力。

公开(公告)号：US07119729B2

公开(公告)日：2006-10-10

申请号：US11060306

申请日：2005-02-18

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

IPC分类号： H03M1/38

CPC分类号： H03M1/164 ,  H03M1/162

摘要： A first analog-digital converter circuit in a preceding stage converts an input analog signal into a digital value and retrieves the higher 4 bits. A second analog-digital converter circuit in a subsequent stage converts an input analog signal into a digital value and retrieves 3 bits including the 5th through 6th highest bits and a redundant bit, 3 bits including the 7th through 8th highest bits and a redundant bit, and 3 bits including the 9th through 10th highest bits and a redundant bit. Thus, the number of bits produced by conversion by the second analog-digital converter circuit in the subsequent stage of a cyclic type is configured to be smaller than the number of bits produced by conversion by the first analog-digital converter circuit in the preceding stage.

摘要翻译： 前一级的第一模数转换器电路将输入的模拟信号转换为数字值，并检索较高的4位。 后续阶段的第二模拟数字转换器电路将输入的模拟信号转换为数字值，并且检索包括第5至第6高位的3位和冗余位，包括第7位至第8位的3位和冗余位， 并且包括第9到第10最高位的3位和冗余位。 因此，通过第二模拟数字转换器电路在循环类型的后续阶段的转换而产生的位数被配置为小于由前一级中的第一模数转换器电路的转换产生的位数 。

公开(公告)号：US07088277B2

公开(公告)日：2006-08-08

申请号：US10945924

申请日：2004-09-22

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/162 ,  H03M1/365

摘要： A cyclic AD converter having a conversion processing speed or conversion accuracy designed no higher than necessary. In the AD converter, an input analog signal is held by a sample-and-hold circuit, and converted into a digital value by an AD conversion circuit. A DA conversion circuit converts the digital value output from the AD conversion circuit into an analog value. A subtractor circuit outputs the difference between the analog value output from the AD conversion circuit and the analog value held in the sample-and-hold circuit. An amplifier circuit amplifies the output of the subtractor circuit, and feeds back the resultant to the sample-and-hold circuit and the AD conversion circuit. In the course of this feedback-based cyclic processing, an amplification control circuit changes the gain of the amplifier circuit in accordance with the progress of the circulation.

摘要翻译： 一种循环AD转换器，其转换处理速度或转换精度设定为不必要。 在AD转换器中，输入模拟信号由采样保持电路保持，并由AD转换电路转换为数字值。 DA转换电路将从AD转换电路输出的数字值转换为模拟值。 减法器电路输出从AD转换电路输出的模拟值与保持在采样保持电路中的模拟值之间的差。 放大器电路放大减法器电路的输出，并将结果反馈到采样保持电路和AD转换电路。 在基于反馈的循环处理的过程中，放大控制电路根据循环的进行改变放大器电路的增益。

公开(公告)号：US07084803B2

公开(公告)日：2006-08-01

申请号：US11047706

申请日：2005-02-02

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/16 ,  H03M1/44

CPC分类号： H03M1/167 ,  H03M1/162

摘要： A first amplifier circuit amplifies an input signal by a factor of α. A first AD converter circuit is configured at an LSB voltage of VA and converts an input analog signal into a digital value of arbitrary N1 bits. A first DA converter circuit converts the digital value output from the first AD converter circuit into an analog signal. A subtracter circuit subtracts an output of the first DA converter circuit from an output of the first subtracter circuit. A second amplifier circuit amplifies an output of the subtracter circuit by a factor of β. A second AD converter is configured at an LSB voltage of VB and converts an input analog signal into a digital value of arbitrary N2 bits. In this circuit, the relation VA*α*β=VB*2N2 holds.

摘要翻译： 第一放大器电路以α的因子放大输入信号。 第一AD转换器电路配置为VA的LSB电压，并将输入的模拟信号转换成任意N 1位的数字值。 第一DA转换器电路将从第一AD转换器电路输出的数字值转换为模拟信号。 减法电路从第一减法器电路的输出中减去第一DA转换器电路的输出。 第二放大器电路将减法器电路的输出放大倍数为β。 第二AD转换器配置为VB的LSB电压，并将输入模拟信号转换为任意N 2位的数字值。 在该电路中，VA *α*β= VB * 2 N 2的关系成立。

公开(公告)号：US07002507B2

公开(公告)日：2006-02-21

申请号：US10945880

申请日：2004-09-22

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/14 ,  H03M1/40

CPC分类号： H03M1/1225 ,  H03M1/162 ,  H03M1/167

摘要： A need exists to provide an AD converter which is well balanced between an increase in processing speed and a decrease in circuit area. The AD converter performs an analog-to-digital conversion separately in four steps, while performing pipelined processing on an AD conversion of the first stage by a first AD conversion circuit and AD conversions of the second to fourth steps by a second AD conversion circuit. A DA conversion circuit, a subtractor circuit, and an amplifier circuit are utilized in a DA conversion, subtraction, and amplification in the first step as well as in DA conversions, subtractions, and amplifications in the second to fourth steps, thus shared in all the steps.

摘要翻译： 需要提供在处理速度的提高和电路面积的减小之间良好平衡的AD转换器。 AD转换器分四步执行模数转换，同时通过第一AD转换电路对第一级的AD转换进行流水线处理，并通过第二AD转换电路对第二至第四步进行AD转换。 在第一步中的DA转换，减法和放大以及第二至第四步中的DA转换，减法和放大中都使用DA转换电路，减法器电路和放大器电路，因此共享 步骤。