公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US07898449B2

公开(公告)日：2011-03-01

申请号：US12562664

申请日：2009-09-18

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20090146854A1

公开(公告)日：2009-06-11

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/12

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US07612700B2

公开(公告)日：2009-11-03

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US08692701B2

公开(公告)日：2014-04-08

申请号：US13599195

申请日：2012-08-30

申请人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

发明人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

IPC分类号： H03M1/38

CPC分类号： H03M1/06 ,  H03M1/167

摘要： A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

摘要翻译： 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容进行采样，保持和放大输入信号。

公开(公告)号：US08730382B2

公开(公告)日：2014-05-20

申请号：US12995913

申请日：2009-06-04

申请人： Chiaki Aoyama ,  Shoji Kawahito

发明人： Chiaki Aoyama ,  Shoji Kawahito

IPC分类号： H04N5/335 ,  G02B7/40

CPC分类号： H01L27/14603 ,  H04N5/2354 ,  H04N5/335 ,  H04N5/37452

摘要： Charge generated in a photodiode is properly split for difference processing. An imaging element is constituted by a semiconductor such that a charge accumulation portion is connected to a light receiving portion using a buried photodiode and charge is split from the charge accumulation portion by a plurality of gates and is accumulated. An imaging device includes a control device performing control so as to accumulate charge that is generated by a photoelectric conversion at an exposure cycle synchronous with the light emission of a light source. The exposure cycle includes a first period for receiving reflection light from a subject illuminated by light from the light source and a second period for receiving light from the subject illuminated by an environmental light not including the light from the light source. The imaging device includes a charge accumulation region connected to each photoelectric conversion region, a first charge storage region for receiving charge generated in the photoelectric conversion regions during the first period via the charge accumulation portion, and a second charge storage region for receiving charge generated in the photoelectric conversion regions during the second period via the charge accumulation portion.

摘要翻译： 在光电二极管中产生的电荷被适当地分开以进行差分处理。 成像元件由半导体构成，使得电荷累积部分使用掩埋光电二极管连接到光接收部分，并且电荷通过多个栅极从电荷累积部分分离，并被累积。 成像装置包括控制装置，其进行控制，以便以与光源的发光同步的曝光周期累积由光电转换产生的电荷。 曝光周期包括用于接收来自被来自光源的光照射的被摄体的反射光的第一周期和用于接收来自被摄体的光的第二周期，所述第二周期由不包括来自光源的光的环境光照射。 成像装置包括连接到每个光电转换区域的电荷累积区域，用于经由电荷累积部分在第一周期期间接收在光电转换区域中产生的电荷的第一电荷存储区域和用于接收 经由电荷累积部分在第二周期期间的光电转换区域。

公开(公告)号：US20120301150A1

公开(公告)日：2012-11-29

申请号：US13577112

申请日：2011-02-04

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H04B10/10

CPC分类号： H01L27/14609 ,  H01L21/28282 ,  H01L27/1443 ,  H01L27/14656 ,  H04N5/3745

摘要： A optical-information acquisition element encompasses a semiconductor layer (31) of a p-type, a surface-buried region (33) of a n-type buried in the semiconductor layer (31) so as to implement a photodiode with the semiconductor layer (31), a charge-accumulation region (36) of the n-type buried in the surface-buried region (33), configured to accumulate charges generated by the photodiode, a barrier-creating region of the p-type buried in the surface-buried region (33) so as to sandwich the surface-buried region (33) with the semiconductor layer (31), configured to create a potential barrier, and a charge-exhaust region (34) of the n-type buried in the semiconductor layer (31), configured to store and to extract excess charges which surmount the potential barrier and flow out from the charge-accumulation region (36). The changes of potential level of the charge-accumulation region (36) are extracted as signals, after receiving optical-communication signals. An optical-information-acquisition element array and a hybrid solid-state imaging device are also provided.

摘要翻译： 光信息采集元件包括埋置在半导体层（31）中的p型半导体层（31），埋入n型的表面埋入区（33），以便实现具有半导体层 （31），掩埋在所述表面埋藏区域（33）中的n型电荷蓄积区域（36），其被配置为积聚由所述光电二极管产生的电荷，所述p型掩埋产生区域 表面埋藏区域（33），以与被形成势垒的半导体层（31）夹着表面埋入区域（33），以及埋入n型的充电排出区域（34） 所述半导体层（31）被配置为存储和提取超过所述势垒并从所述电荷累积区域（36）流出的过量电荷。 在接收到光通信信号之后，电荷累积区域（36）的电位电平的变化被提取为信号。 还提供了光学信息采集元件阵列和混合固态成像装置。

公开(公告)号：US20120104235A1

公开(公告)日：2012-05-03

申请号：US13344090

申请日：2012-01-05

申请人： Hirofumi Sumi ,  Nobuo Nakamura ,  Shoji Kawahito

发明人： Hirofumi Sumi ,  Nobuo Nakamura ,  Shoji Kawahito

IPC分类号： H01L27/146

CPC分类号： H04N5/3575 ,  H04N5/243 ,  H04N5/3696 ,  H04N5/37455 ,  H04N5/37457

摘要： A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

摘要翻译： 包括像素信号控制器的固态成像装置的前置放大器（列区域单元）。 像素信号控制器对于每个垂直信号线，由像素信号放大器的输出侧的像素信号检测器独立地检测每个像素信号的电平，并且根据图像信号放大器独立地设置增益 信号的电平。 在固态成像装置的后续阶段，提供了模数（A / D）转换器和信号延伸单元。 A / D转换器对像素信号进行数字化，参照来自像素信号检测器的分类信号，通过设置到像素信号放大器的增益来校正数字化像素信号，使得一个屏幕的信号的动态范围 延长了

公开(公告)号：US20110298079A1

公开(公告)日：2011-12-08

申请号：US13142141

申请日：2009-12-25

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H01L31/02

CPC分类号： H01L27/14603 ,  H01L27/14612 ,  H01L27/14689 ,  H04N5/374

摘要： A semiconductor element includes: a p-type semiconductor region; an n-type light-receiving surface buried region buried in the semiconductor region; an n-type charge accumulation region buried in the semiconductor region, continuously to the light-receiving surface buried region, establishing a deeper potential well depth than the light-receiving surface buried region; a charge read-out region configured to read out the charges accumulated in the charge accumulation region; an exhaust-drain region buried in the semiconductor region, configured to extract the charges from the light-receiving surface buried region; a first potential controller configured to extract the charges from the light-receiving surface buried region to the exhaust-drain region; and a second potential controller configured to transfer the charges from the charge accumulation region to the charge read-out region.

摘要翻译： 半导体元件包括：p型半导体区域; 埋在半导体区域中的n型光接收表面掩埋区域; 埋置在半导体区域中的n型电荷累积区域，连续地连接到受光面掩埋区域，形成比受光面埋藏区域更深的势阱深度; 电荷读出区域，被配置为读出在电荷累积区域中累积的电荷; 埋置在所述半导体区域中的废气排放区域，被配置为从所述受光面掩埋区域提取电荷; 第一电位控制器，被配置为从所述光接收表面掩埋区域提取到所述排气区域的电荷; 以及第二电位控制器，被配置为将电荷从电荷累积区域转移到电荷读出区域。

公开(公告)号：US20110157354A1

公开(公告)日：2011-06-30

申请号：US13056697

申请日：2009-07-30

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H04N7/18

CPC分类号： H01L27/14603 ,  G01S7/4863 ,  G01S17/10 ,  G01S17/89 ,  H01L31/02024 ,  H04N5/341 ,  H04N13/254

摘要： A distance image sensor capable of enlarging the distance measurement range without reducing the distance resolution is provided. A radiation source 13 provides first to fifth pulse trains PT1 to PT5 which are irradiated to the object as radiation pulses in the first to fifth frames arranged in order on a time axis. In each of the frames, imaging times TPU1 to TPU5 are prescribed at points of predetermined time ΔTPD from the start point of each frame, also the pulses PT1 to PT5 are shifted respectively by shift amounts different from each other from the start point of the first to fifth frames. A pixel array 23 generates element image signals SE1 to SE5 each of which has distance information of an object in distance ranges different from each other using imaging windows A and B in each of five frames. A processing unit 17 generates an image signal SIMAGE by combining the element image signals. Since five times-of-flight measurement are used, the width of the radiation pulse does not have to be increased to obtain distance information of the object in a wide distance range, and the distance resolution is not reduced.

摘要翻译： 提供了能够在不减小距离分辨率的情况下扩大距离测量范围的距离图像传感器。 辐射源13提供照射到物体的第一至第五脉冲串PT1至PT5，作为在时间轴上按顺序布置的第一至第五帧中的辐射脉冲。 在每个帧中，从每帧开始点的预定时间＆Dgr; TPD的点处规定成像时间TPU1〜TPU5，脉冲PT1〜PT5也分别移动与起始点不同的移动量 第一到第五帧。 像素阵列23使用五帧中的每一帧中的成像窗口A和B，生成各自具有彼此不同的距离范围的对象的距离信息的元素图像信号SE1〜SE5。 处理单元17通过组合元素图像信号来生成图像信号SIMAGE。 由于使用五次飞行测量，所以不必增加辐射脉冲的宽度，以获得物体在较宽距离范围内的距离信息，并且距离分辨率不降低。