公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

申请人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12 ,  H03F3/45

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20090278716A1

公开(公告)日：2009-11-12

申请号：US12436289

申请日：2009-05-06

申请人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

发明人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US20130057418A1

公开(公告)日：2013-03-07

申请号：US13599195

申请日：2012-08-30

申请人： Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

发明人： Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/167

摘要： A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

摘要翻译： 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容采样，保持和放大输入信号。

公开(公告)号：US20120153130A1

公开(公告)日：2012-06-21

申请号：US13406340

申请日：2012-02-27

申请人： Nobuo NAKAMURA ,  Shoji KAWAHITO ,  Hiroki SATO ,  Mizuho HIGASHI

发明人： Nobuo NAKAMURA ,  Shoji KAWAHITO ,  Hiroki SATO ,  Mizuho HIGASHI

IPC分类号： H01L27/148

CPC分类号： H04N5/378 ,  H01L27/14609 ,  H04N5/243 ,  H04N5/355 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/37457

摘要： An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

摘要翻译： 图像传感器在逐像素的基础上控制像素信号的增益，并且在保持S / N比在有利的水平的同时延伸动态范围。 图像传感器中的列单元独立地检测每个像素信号的电平，并独立地设置信号电平的增益。 光电转换区域单元具有用于每个像素列的垂直信号线二维布置的像素，以输出每个像素信号。 列单元位于垂直信号线的输出侧。 每个像素列的列单元具有像素信号电平检测电路，可编程增益控制，采样和保持（S / H）电路。 根据检测到的像素信号电平的结果进行增益校正。

公开(公告)号：US20110031543A1

公开(公告)日：2011-02-10

申请号：US12907705

申请日：2010-10-19

申请人： Shoji KAWAHITO

发明人： Shoji KAWAHITO

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14656 ,  H04N5/35518 ,  H04N5/3598

摘要： An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

摘要翻译： 作为光电二极管的电荷存储区域的n型区域埋在基板中。 硅和氧化硅膜之间的界面被高浓度p层覆盖，并且较低浓度的p层仅形成在用于信号提取的浮动电极正下方的部分。 由光产生的电子被存储在电荷存储区域中，从而改变在半导体区域的表面处的p层的部分的电位。 该变化通过电容耦合通过薄的绝缘膜透射到浮动电极，并由缓冲晶体管读出。 通过向第一传输晶体管的栅极添加正高电压，使得存储在电荷存储区域中的电子被转移到n +区域并且产生复位噪声被保护来执行电荷的初始化。

公开(公告)号：US20110025420A1

公开(公告)日：2011-02-03

申请号：US12903333

申请日：2010-10-13

申请人： Hirofumi SUMI ,  Nobuo NAKAMURA ,  Shoji KAWAHITO

发明人： Hirofumi SUMI ,  Nobuo NAKAMURA ,  Shoji KAWAHITO

IPC分类号： H03G3/00

CPC分类号： H04N5/3575 ,  H04N5/243 ,  H04N5/3696 ,  H04N5/37455 ,  H04N5/37457

摘要： A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

摘要翻译： 包括像素信号控制器的固态成像装置的前置放大器（列区域单元）。 像素信号控制器对于每个垂直信号线，由像素信号放大器的输出侧的像素信号检测器独立地检测每个像素信号的电平，并且根据图像信号放大器独立地设置增益 信号的电平。 在固态成像装置的后续阶段，提供了模数（A / D）转换器和信号延伸单元。 A / D转换器对像素信号进行数字化，参照来自像素信号检测器的分类信号，通过设置到像素信号放大器的增益来校正数字化像素信号，使得一个屏幕的信号的动态范围 延长了