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公开(公告)号：US06836022B2
公开(公告)日：2004-12-28
申请号：US10365765
申请日：2003-02-13
IPC分类号： H01L2348
CPC分类号： H01L23/552 , H01L21/563 , H01L23/585 , H01L29/0619 , H01L2224/16 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： A flip-chip package comprises a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.
摘要翻译： 倒装芯片封装包括具有至少一个层的衬底和安装到衬底的部件倒装芯片，该部件具有场终端环。 倒装芯片封装还包括插入在至少一层衬底和场终端环之间的屏蔽平面。
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公开(公告)号：US20130335937A1
公开(公告)日：2013-12-19
申请号：US13524368
申请日：2012-06-15
IPC分类号： H05K1/18
CPC分类号： H01L25/00 , A61N1/3758 , A61N1/3968 , H01F27/2804 , H01F2027/2819 , H01L23/647 , H01L25/16 , H01L2924/0002 , H01L2924/00
摘要： A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.
摘要翻译： 用于可植入医疗器件的晶片级封装中的混合集成电路包括至少部分地沿着封装的一个或多个布线层形成的一个或多个无源元件绕组。 绕组可以是变压器的初级和次级绕组，其中全部或部分磁芯嵌入在晶片级封装的组件层中。 如果芯包括结合到包装表面的部分，那么芯部的该部分可以是E形的，其中腿部延伸到路线层中，并且在一些情况下，可以通过路由层。 在某些情况下，路由层可以形成在组件层的两侧以容纳变压器绕组。
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3.发明授权Feedthrough assembly for implantable medical devices and methods for providing same 有权用于可植入医疗器械的馈通组件及其提供方法
公开(公告)号：US6052623A
公开(公告)日：2000-04-18
申请号：US201059
申请日：1998-11-30
IPC分类号： A61N1/375
CPC分类号： A61N1/3754
摘要： A feedthrough assembly for an implantable medical device includes one or more electrically conductive pins extending through apertures in a case of the medical device with the electrically conductive pins being insulated from the case. The feedthrough assembly further includes a printed circuit board having a diode protection circuit mounted thereon. The printed circuit board forms at least a part of electrically conductive paths for connection of the electrically conductive pins to a medical device circuit assembly mounted within the case. The printed circuit board further provides for electrical connection of the diode protection circuit mounted thereon between the electrically conductive pins and the case.
摘要翻译： 用于可植入医疗装置的馈通组件包括在医疗装置的壳体中延伸穿过孔的一个或多个导电销，其中导电销与壳体绝缘。 馈通组件还包括其上安装有二极管保护电路的印刷电路板。 印刷电路板形成用于将导电针连接到安装在壳体内的医疗装置电路组件的导电路径的至少一部分。 印刷电路板还提供安装在其上的二极管保护电路在导电引脚和外壳之间的电连接。
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公开(公告)号：US07167074B2
公开(公告)日：2007-01-23
申请号：US11034323
申请日：2005-01-12
IPC分类号： H01F5/00
CPC分类号： H01F27/2804 , A61N1/3956 , H01F2027/2819
摘要： Method and apparatus are provided for fabricating a planar transformer assembly for use in an implantable medical device. The planar transformer assembly includes a board, a first core, and a second core. The board has a first side, a second side, and an embedded winding, wherein the embedded winding includes a primary winding and a secondary winding and is at least partially embedded in the board between the first and second sides.
摘要翻译： 提供了用于制造用于可植入医疗装置的平面变压器组件的方法和装置。 平面变压器组件包括板，第一芯和第二芯。 该板具有第一面，第二面和嵌入式绕组，其中嵌入式绕组包括初级绕组和次级绕组，并且至少部分地嵌入在第一和第二侧之间的板中。
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公开(公告)号：US06707065B2
公开(公告)日：2004-03-16
申请号：US10243264
申请日：2002-09-16
IPC分类号： H01L2358
CPC分类号： G01R31/2831 , G01R31/316
摘要： In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
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6.发明授权公开(公告)号：US09252415B2
公开(公告)日：2016-02-02
申请号：US13524304
申请日：2012-06-15
IPC分类号： H01M2/10 , H01M2/20 , H01M2/24 , H01M2/26 , H01M10/0562 , H01M10/0585 , H01M10/647 , H01M6/40 , H01M6/46 , H01M2/22 , H01M10/04 , H01M10/0525 , A61N1/378 , A61N1/375
CPC分类号： H01M2/204 , A61N1/3758 , A61N1/378 , H01M2/1066 , H01M2/202 , H01M2/22 , H01M2/24 , H01M2/266 , H01M6/40 , H01M6/46 , H01M10/0436 , H01M10/0525 , H01M10/0562 , H01M10/0585 , H01M10/647 , Y02E60/122 , Y10T29/49112
摘要： Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.
摘要翻译： 平面固态电池的阵列以对准的布置堆叠，以便随后分离成单独的电池堆叠。 在堆叠之前，在包含阵列的每个晶片的表面上形成重分布层（RDL）; 每个RDL包括第一和第二组导电迹线，每个导体迹线首先从对应的正电池触点横向延伸，并且每个第二组从相应的负电池触点横向延伸。 在堆叠之前或之后形成的导电通孔最终将对准的电池的相应触点耦合在一起。 如果之前，每个通孔延伸穿过每个晶片的对应的电池触点并且耦合到相应的导电层，该导电层被包括在形成于每个晶片的相对表面上的另一个RDL中。 如果之后，每个通孔延伸通过对应的对准的导电迹线，并且在单独的电池堆分离时，成为相应电池堆的暴露的导电通道。
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公开(公告)号：US07196889B2
公开(公告)日：2007-03-27
申请号：US10298134
申请日：2002-11-15
IPC分类号： H02H9/00
CPC分类号： H01L27/0255
摘要： An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate.A Zener diode is coupled to a second terminal of the switchable device to trigger the switchable device to a conducting state. The Zener diode is formed in the same doped region of the substrate as the trigger of the switchable device.
摘要翻译： 在具有用于形成半导体器件的多个掺杂区域的半导体衬底中形成过电压保护器件。 过电压保护装置适于将电流从设备中抽出以防止过电压，并且具有可切换装置，其具有适于耦合到潜在的过电压源的端子和用于将电流从电位引出的电流 触发可切换装置时的过电压源，以及将电流引导到半导体衬底。
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8.发明授权Method and apparatus for wafer-level burn-in and testing of integrated circuits 失效用于晶圆级老化和集成电路测试的方法和装置公开(公告)号：US06806494B2
公开(公告)日：2004-10-19
申请号：US10445547
申请日：2003-05-27
IPC分类号： H01L2358
CPC分类号： G01R31/2831 , G01R31/316
摘要： In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
摘要翻译： 在一个实施方案中，实施测试方案以减少测试时间。 具体地说，实现了在测试每个管芯之前对晶片上的所有管芯加电和稳定的结构和方法。 更具体地，使用包括管芯稳定程序的并行供电方案来准备晶片进行测试。 晶圆探针测试仪从一个芯片转移到另一个芯片，以便在所有芯片上电和稳定之后对晶片中的所有裸片进行不间断的测试。
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公开(公告)号：US06548826B2
公开(公告)日：2003-04-15
申请号：US09815031
申请日：2001-03-22
IPC分类号： H01L2358
CPC分类号： G01R31/2831 , G01R31/316
摘要： In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
摘要翻译： 在一个实施方案中，实施测试方案以减少测试时间。 具体地说，实现了在测试每个管芯之前对晶片上的所有管芯加电和稳定的结构和方法。 更具体地，使用包括管芯稳定程序的并行供电方案来准备晶片进行测试。 晶圆探针测试仪从一个芯片转移到另一个芯片，以便在所有芯片上电和稳定之后对晶片中的所有裸片进行不间断的测试。
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公开(公告)号：US08824161B2
公开(公告)日：2014-09-02
申请号：US13524368
申请日：2012-06-15
IPC分类号： H05K7/00
CPC分类号： H01L25/00 , A61N1/3758 , A61N1/3968 , H01F27/2804 , H01F2027/2819 , H01L23/647 , H01L25/16 , H01L2924/0002 , H01L2924/00
摘要： A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.
摘要翻译： 用于可植入医疗器件的晶片级封装中的混合集成电路包括至少部分地沿着封装的一个或多个布线层形成的一个或多个无源元件绕组。 绕组可以是变压器的初级和次级绕组，其中全部或部分磁芯嵌入在晶片级封装的组件层中。 如果芯包括结合到包装表面的部分，那么芯部的该部分可以是E形的，其中腿部延伸到路线层中，并且在一些情况下，可以通过路由层。 在某些情况下，路由层可以形成在组件层的两侧以容纳变压器绕组。
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