公开(公告)号：US4774198A

公开(公告)日：1988-09-27

申请号：US19785

申请日：1987-02-26

申请人： Claudio Contiero ,  Antonio Andreini ,  Paola Galbiati

发明人： Claudio Contiero ,  Antonio Andreini ,  Paola Galbiati

IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L29/10 ,  H01L21/425

CPC分类号： H01L29/66719 ,  H01L21/0337 ,  H01L29/1095 ,  H01L29/66712

摘要： An improved fabrication process for vertical DMOS cells contemplates the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, also allowing the forming the source region. Opening of the relative contact is also effected by a self alignment technique, further simplifying the process.

摘要翻译： 用于垂直DMOS单元的改进的制造工艺考虑了通过放置多晶硅栅电极并利用栅电极本身作为用于植入和扩散体区的掩模的先前定义的栅极区域，同时使用自身进行形成短区域 对准技术，其允许容易地控制区域本身的横向延伸。 非临界掩模定义了在源极电极和DMOS电池中间的源极和体区之间的短路接触将被制成的区域，也允许形成源极区域。 相对接触的打开也通过自对准技术进行，进一步简化了过程。

公开(公告)号：US4892836A

公开(公告)日：1990-01-09

申请号：US028842

申请日：1987-03-23

申请人： Antonio Andreini ,  Claudio Contiero ,  Paola Galbiati

发明人： Antonio Andreini ,  Claudio Contiero ,  Paola Galbiati

IPC分类号： H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/8236 ,  H01L21/033 ,  H01L21/823456 ,  H01L27/0922

摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

摘要翻译： 该方法需要减少数量的工艺阶段并提供有效的高电压结构，包括通过硼原子注入通过保护掩模形成CMOS器件的N沟道晶体管的P阱区域，形成 围绕所述CMOS器件的至少一个绝缘区域，形成具有与所述绝缘区域相同的导电类型但在所述绝缘区域的至少一部分上以及所述高压电子器件中的较小的杂质浓度的边缘区域，借助于所述绝缘区域 用于形成P阱区的相同的硼原子注入。

公开(公告)号：US4721686A

公开(公告)日：1988-01-26

申请号：US6037

申请日：1987-01-22

申请人： Claudio Contiero ,  Paola Galbiati ,  Antonio Andreini

发明人： Claudio Contiero ,  Paola Galbiati ,  Antonio Andreini

IPC分类号： H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/38 ,  H01L21/425

CPC分类号： H01L21/8249 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/2652 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238

摘要： This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.

摘要翻译： 相对于已知方法需要较少数量的掩模步骤的该方法包括通过适当的掩模在外延层的表面上的硼注入而不进行掩模，并且在外延层表面的预定位置进行砷注入。 然后随后的热处理导致注入的砷和硼原子的扩散，但是通过与后者的相互作用来防止在其中也发生砷注入的区域中的硼扩散，从而获得具有N +型导电性的区域，其中两个硼 已经植入了砷，并且仅植入硼的P型导电性区域。

公开(公告)号：US06093588A

公开(公告)日：2000-07-25

申请号：US18410

申请日：1998-02-04

申请人： Riccardo De Petro ,  Paola Galbiati ,  Michele Palmieri ,  Claudio Contiero

发明人： Riccardo De Petro ,  Paola Galbiati ,  Michele Palmieri ,  Claudio Contiero

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/7813 ,  H01L29/42368

摘要： A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication.To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

摘要翻译： 与形成在单晶硅层上的各种相互交错的模块化元件构成的高电压横向MOSFET晶体管结构与其制造方法一起被描述。 为了节省硅的面积并降低掺杂漏极区域的电阻率RDS，通过在通过选择性各向异性蚀刻获得的场氧化物中的孔中注入掺杂材料形成掺杂材料，通过将作为掩模的多晶硅的条用作 栅电极和场电极。

公开(公告)号：US5589405A

公开(公告)日：1996-12-31

申请号：US403629

申请日：1995-04-21

申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

IPC分类号： H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L49/00

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S148/053 ,  Y10S148/126

摘要： The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

摘要翻译： VDMOS晶体管的击穿电压显着增加，而不会通过将源极单元阵列与漏极扩散区分开形成在场氧化物带的边缘部分下面的场隔离扩散电位来抑制器件的其它电气特性 ，到晶体管的源极电位。 这可以通过将外围源电池的体区域延伸到每隔给定数量的外围电池单元面向磁场隔离结构条带直到其与所述场隔离扩散相交的方式来实现。 通过这样连接每个给定数量的单元的一个外围源单元，集成晶体管的总体通道宽度的实际减小可以忽略不计，从而保留功率晶体管的电气特性。

公开(公告)号：US5430316A

公开(公告)日：1995-07-04

申请号：US19124

申请日：1993-02-17

申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

IPC分类号： H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S148/053 ,  Y10S148/126

摘要： The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

摘要翻译： VDMOS晶体管的击穿电压显着增加，而不会通过将源极单元阵列与漏极扩散分离的场氧化物条带的边缘部分下方形成的场隔离扩散电位相扣合来抑制器件的其它电气特性 ，到晶体管的源极电位。 这可以通过将外围源电池的体区域延伸到每隔给定数量的外围电池单元面向磁场隔离结构条带直到其与所述场隔离扩散相交的方式来实现。 通过这样连接每个给定数量的单元的一个外围源单元，集成晶体管的总体通道宽度的实际减小可以忽略不计，从而保留功率晶体管的电气特性。

公开(公告)号：US4949142A

公开(公告)日：1990-08-14

申请号：US773316

申请日：1985-09-06

申请人： Claudio Contiero ,  Paola Galbiati

发明人： Claudio Contiero ,  Paola Galbiati

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/088

摘要： The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.

摘要翻译： 所公开的桥式电路使用功率MOS技术制造。 桥接电路的公共端子在实现中被集成到公共区域中。 通常在桥式电路中耦合在一起的电极由半导体芯片的集成电路中的共用导电区域实现。 通过集成电路的元件，与涉及4（4）个分立元件的实现相比，需要较少的半导体芯片面积。 二极管跨越晶体管制造，以保护元件免受反向偏置。

公开(公告)号：US5081517A

公开(公告)日：1992-01-14

申请号：US548711

申请日：1990-07-06

申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CDES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

摘要翻译： 高密度，混合技术的集成电路包括CMOS结构和双极横向晶体管，通过在收集器区域形成“阱”区域，电效率和早期电压保持较高。 该操作确定在外延层内形成相对较深的“集电极延伸区域”，以便截取发射极电流并将其收集到集电极，并将其从色散向衬底通过围绕着该区域的相邻隔离结 横向双极晶体管。 在可比较的条件下，IcI衬底之间的比例从大约8增加到大约300，而早期电压从大约20V增加到大约100V。 VCEO，BVCBO和BVCDES电压也有利地通过在收集器区域中形成的所述“阱”区域的存在来增加。

公开(公告)号：USRE37424E1

公开(公告)日：2001-10-30

申请号：US08943326

申请日：1997-10-03

申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

IPC分类号： H01L2906

CPC分类号： H01L27/0922 ,  H01L27/0623

摘要： Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any “level shifting” stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

摘要翻译： 可以在所谓的“智能电源”类型的混合技术集成电路中实现能够承受相对高的电压的互补LDMOS和MOS结构以及垂直PNP晶体管，通过形成具有相似扩散曲线的磷掺杂n区 ，分别为：n沟道LDMOS晶体管的漏极区，在p沟道LDMOS晶体管的体区形成第一个CMOS结构; 在属于第二CMOS结构的n沟道MOS晶体管的漏极区域和靠近隔离集电极的发射极区域的基极区域中，垂直PNP晶体管，从而同时实现所有这些单片集成结构的耐压能力的提高的结果。 互补LDMOS结构可以用作具有降低的导通电阻的功率结构，或者可以用于实现能够在相对高的电压（约20V）下工作的CMOS级，从而允许与VDMOS功率器件的直接接口，而不需要任何“ 水平转变“阶段。 整个集成电路具有较少的接口问题和改善的电气和可靠性特性。

公开(公告)号：US6022778A

公开(公告)日：2000-02-08

申请号：US612722

申请日：1996-03-08

申请人： Claudio Contiero ,  Paola Galbiati ,  Michele Palmieri

发明人： Claudio Contiero ,  Paola Galbiati ,  Michele Palmieri

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/115 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66659 ,  H01L21/823456 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66674 ,  H01L29/7816 ,  H01L29/0847

摘要： A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

摘要翻译： 用于制造具有DMOS技术功率器件和非易失性存储器单元的集成电路的工艺提供了形成相互电绝缘的相互横向偏移的隔离半导体区域以及将形成器件的共用半导体衬底 ; 形成用于DMOS技术功率器件和各个隔离半导体区域上的存储器单元的导电栅极区域。 在用于DMOS技术功率器件的隔离半导体区域内部，形成在绝缘栅极区域下延伸的沟道区域。 通过以剂量和能量使掺杂剂沿相对于与集成电路的顶表面正交的方向倾斜规定角度的方向注入形成沟道区，使得沟道区直接形成在 注入掺杂剂而不在掺杂剂的高温下进行热扩散。