公开(公告)号：US20090172283A1

公开(公告)日：2009-07-02

申请号：US12006287

申请日：2007-12-31

Applicant: Muhammad M. Khellah ,  Christopher Wilkerson ,  Alaa R. Alameldeen ,  Bibiche M. Geuskens ,  Tanay Karnik ,  Vivek De ,  Gunjan H. Pandya

Inventor： Muhammad M. Khellah ,  Christopher Wilkerson ,  Alaa R. Alameldeen ,  Bibiche M. Geuskens ,  Tanay Karnik ,  Vivek De ,  Gunjan H. Pandya

IPC: G06F12/08

CPC classification number: G11C5/14 ,  G06F12/0802 ,  G06F2212/1028 ,  G11C11/412 ,  G11C11/413 ,  Y02D10/13

Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.

Abstract translation: 描述了通过混合高速缓存设计降低最小工作电压的方法和装置。 在一个实施例中，可以使用具有不同大小的位单元的高速缓存，例如以减少包括高速缓存和可能的其它逻辑（例如处理器）的集成电路设备的最小工作电压。 还描述了其它实施例。

公开(公告)号：US20120110266A1

公开(公告)日：2012-05-03

申请号：US13342016

申请日：2011-12-31

Applicant: Christopher Wilkerson ,  M. Muhammad Khellah ,  Vivek De ,  Ming Y. Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

Inventor： Christopher Wilkerson ,  M. Muhammad Khellah ,  Vivek De ,  Ming Y. Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0864 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract translation: 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。

公开(公告)号：US08103830B2

公开(公告)日：2012-01-24

申请号：US12242321

申请日：2008-09-30

Applicant: Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/16

CPC classification number: G06F12/0895 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0864 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract translation: 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。

公开(公告)号：US20100257529A1

公开(公告)日：2010-10-07

申请号：US12384501

申请日：2009-04-06

Applicant: Christopher Wilkerson ,  Ming Zhang ,  Wei Wu

Inventor： Christopher Wilkerson ,  Ming Zhang ,  Wei Wu

IPC: G06F9/46 ,  H02J7/35

CPC classification number: H02J7/345 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/4893 ,  H02J7/35 ,  Y02D10/24

Abstract: With some embodiments, task processing based on power availability is provided for mobile computing platforms including laptops, tablets, netbooks, cell phones, as well as for other devices or systems that are not mobile such as desktop computers and server systems.

Abstract translation: 对于一些实施例，基于功率可用性的任务处理被提供给包括笔记本电脑，平板电脑，上网本，蜂窝电话以及不是诸如台式计算机和服务器系统之类的移动设备的其他设备或系统的移动计算平台。

公开(公告)号：US20100082905A1

公开(公告)日：2010-04-01

申请号：US12242321

申请日：2008-09-30

Applicant: Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0864 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract translation: 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。

公开(公告)号：US20190303162A1

公开(公告)日：2019-10-03

申请号：US15940408

申请日：2018-03-29

Applicant: Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US20180373632A1

公开(公告)日：2018-12-27

申请号：US16056315

申请日：2018-08-06

Applicant: Christopher WILKERSON ,  Ren WANG ,  Antoine KAUFMANN ,  Anil VASUDEVAN ,  Robert G. BLANKENSHIP ,  Venkata KRISHNAN ,  Tsung-Yuan C. Tai

Inventor： Christopher WILKERSON ,  Ren WANG ,  Antoine KAUFMANN ,  Anil VASUDEVAN ,  Robert G. BLANKENSHIP ,  Venkata KRISHNAN ,  Tsung-Yuan C. Tai

IPC: G06F12/0808 ,  G06F12/0891 ,  G06F12/0862

Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.

公开(公告)号：US09229872B2

公开(公告)日：2016-01-05

申请号：US13843639

申请日：2013-03-15

Applicant: Christopher Wilkerson ,  Jawad Nasrullah ,  Kelvin Kwan

Inventor： Christopher Wilkerson ,  Jawad Nasrullah ,  Kelvin Kwan

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G01R31/31724 ,  G01R31/3187 ,  G06F1/3275 ,  G06F1/3296 ,  G06F11/2221 ,  G06F11/27 ,  G06F2212/601 ,  G11C29/16 ,  G11C2029/0401 ,  G11C2029/0409 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Abstract translation: 描述了在半导体管芯的运行时间期间包括嵌入在管芯上的存储部件的下一个BIST测试序列是适当的方法。 该方法还包括将BIST测试序列应用于存储组件中的每个有效条目。 该方法还包括将存储组件中的任何新无效条目标记为无效，并为每个新无效条目配置相应的替换条目。

公开(公告)号：US20140281254A1

公开(公告)日：2014-09-18

申请号：US13843639

申请日：2013-03-15

Applicant: Christopher WILKERSON ,  Jawad NASRULLAH ,  Kelvin KWAN

Inventor： Christopher WILKERSON ,  Jawad NASRULLAH ,  Kelvin KWAN

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G01R31/31724 ,  G01R31/3187 ,  G06F1/3275 ,  G06F1/3296 ,  G06F11/2221 ,  G06F11/27 ,  G06F2212/601 ,  G11C29/16 ,  G11C2029/0401 ,  G11C2029/0409 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Abstract translation: 描述了在半导体管芯的运行时间期间包括嵌入在管芯上的存储部件的下一个BIST测试序列是适当的方法。 该方法还包括将BIST测试序列应用于存储组件中的每个有效条目。 该方法还包括将存储组件中的任何新无效条目标记为无效，并为每个新无效条目配置相应的替换条目。

公开(公告)号：US20060277398A1

公开(公告)日：2006-12-07

申请号：US11145409

申请日：2005-06-03

Applicant: Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

Inventor： Haitham Akkary ,  Ravi Rajwar ,  Srikanth Srinivasan ,  Christopher Wilkerson

IPC: G06F9/44

CPC classification number: G06F9/3836 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

Abstract: A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.

Abstract translation: 公开了一种用于从重排序缓冲器中排除长延迟微操作的方法和装置。 在一个实施例中，长时间延迟微操作通常会阻止重新排序缓冲器。 因此，可以使用辅助缓冲器来临时存储长延迟微操作以及依赖于其的微操作，直到长时间延迟微操作准备好执行。 然后可以将这些微操作重新引入重排序缓冲器中以供执行。 可以使用中毒的位来确保正确地退出从辅助缓冲器中放置的微操作执行之前和之后合并的寄存器值。