公开(公告)号：US08119542B2

公开(公告)日：2012-02-21

申请号：US12495137

申请日：2009-06-30

申请人： Vincent Mevellec ,  José Gonzalez ,  Dominique Suhr

发明人： Vincent Mevellec ,  José Gonzalez ,  Dominique Suhr

IPC分类号： H01L21/31

CPC分类号： H01L21/02118 ,  C25D7/123 ,  C25D13/18 ,  H01L21/02282 ,  H01L21/288 ,  H01L21/312 ,  H01L21/76843 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate.According to the invention, this method comprises: a) bringing said surface into contact with a liquid solution comprising: a protic solvent; at least one diazonium salt; at least one monomer that is chain-polymerizable and soluble in said protic solvent; at least one acid in a sufficient quantity to stabilize said diazonium salt by adjusting the pH of said solution to a value less than 7, preferably less than 2.5; b) the polarization of said surface according to a potentio- or galvano-pulsed mode for a duration sufficient to form a film having a thickness of at least 60 nanometers, and preferably between 80 and 500 nanometers. Application: Metallization of through-vias, especially of 3D integrated circuits.

摘要翻译： 本发明基本上涉及在诸如硅衬底的电导体或半导体衬底的表面上制备电绝缘膜的方法。 根据本发明，该方法包括：a）使所述表面与包含质子溶剂的液体溶液接触; 至少一种重氮盐; 至少一种可聚合并可溶于所述质子溶剂的单体; 至少一种足够量的酸以通过将所述溶液的pH调节至小于7，优选小于2.5的值来稳定所述重氮盐; b）根据电位或电流脉冲模式的所述表面的极化持续足够长的时间以形成厚度为至少60纳米，优选为80至500纳米的膜。 应用：通孔的金属化，特别是3D集成电路的金属化。

公开(公告)号：US09181623B2

公开(公告)日：2015-11-10

申请号：US13390208

申请日：2010-09-09

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： C23C18/30 ,  C23C18/32 ,  C23C18/18 ,  C23C18/16 ,  C23C18/20 ,  H01L21/768

CPC分类号： C23C18/1882 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1879 ,  C23C18/2066 ,  C23C18/30 ,  C23C18/32 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76898

摘要： A solution and a process are used for activating the surface of a substrate comprising at least one area formed from a polymer, for the purpose of subsequently covering it with a metallic layer deposited via an electroless process. The composition contains: A) an activator formed from one or more palladium complexes; B) a binder formed from one or more organic compounds chosen from compounds comprising at least two glycidyl functions and at least two isocyanate functions; and C) a solvent system formed from one or more solvents capable of dissolving said activator and said binder. The solution and process may be applied for the manufacture of electronic devices such as integrated circuits, especially in three dimensions.

摘要翻译： 使用溶液和方法来激活包含由聚合物形成的至少一个区域的基材的表面，以便随后用经由无电镀方法沉积的金属层覆盖该表面。 组合物包含：A）由一种或多种钯络合物形成的活化剂; B）由选自包含至少两个缩水甘油基官能团和至少两个异氰酸酯官能团的化合物的一种或多种有机化合物形成的粘合剂; 和C）由能够溶解所述活化剂和所述粘合剂的一种或多种溶剂形成的溶剂体系。 解决方案和方法可以应用于诸如集成电路的电子设备的制造，特别是在三维中。

公开(公告)号：US20120156892A1

公开(公告)日：2012-06-21

申请号：US13390208

申请日：2010-09-09

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： H01L21/312 ,  B05D5/12 ,  C09D5/00

CPC分类号： C23C18/1882 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1879 ,  C23C18/2066 ,  C23C18/30 ,  C23C18/32 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76898

摘要： The present invention relates to a solution and a process for activating the surface of a substrate comprising at least one area formed from a polymer, for the purpose of subsequently covering it with a metallic layer deposited via an electroless process.According to the invention, this composition contains: A) an activator formed from one or more palladium complexes; B) a binder formed from one or more organic compounds chosen from compounds comprising at least two glycidyl functions and at least two isocyanate functions; C) a solvent system formed from one or more solvents capable of dissolving said activator and said binder. Application: Manufacture of electronic devices such as, in particular, integrated circuits, especially in three dimensions.

摘要翻译： 本发明涉及用于激活基材表面的溶液和方法，其包括由聚合物形成的至少一个区域，以便随后用经由无电镀方法沉积的金属层覆盖该表面。 根据本发明，该组合物包含：A）由一种或多种钯络合物形成的活化剂; B）由选自包含至少两个缩水甘油基官能团和至少两个异氰酸酯官能团的化合物的一种或多种有机化合物形成的粘合剂; C）由能够溶解所述活化剂和所述粘合剂的一种或多种溶剂形成的溶剂体系。 应用：电子设备的制造，特别是集成电路，尤其是三维。

公开(公告)号：US09368397B2

公开(公告)日：2016-06-14

申请号：US14119184

申请日：2012-05-22

申请人： Dominique Suhr ,  Vincent Mevellec

发明人： Dominique Suhr ,  Vincent Mevellec

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L21/02063 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/76823 ,  H01L21/76831 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The invention proposes a method for forming a vertical electrical connection (50) in a layered semiconductor structure (1), comprising the following steps: —providing (100) a layered semiconductor structure (1), said layered semiconductor structure (1) comprising: —a support substrate (20) including an first surface (22) and a second surface (24), —an insulating layer (30) overlying the first surface (22) of the support substrate (20), and —at least one device structure (40) formed in the insulating layer (30); and —drilling (300) a via (50) from the second surface of the support substrate (20) up to the device structure (40), in order to expose the device structure (40); characterized in that drilling (300) of the insulating layer is at least performed by wet etching (320).

摘要翻译： 本发明提出了一种在层状半导体结构（1）中形成垂直电连接（50）的方法，包括以下步骤：提供（100）层状半导体结构（1），所述分层半导体结构（1）包括： - 包括第一表面（22）和第二表面（24）的支撑衬底（20）， - 覆盖所述支撑衬底（20）的第一表面（22）的绝缘层（30），以及 - 至少一个器件 在绝缘层（30）中形成的结构（40）; 以及从所述支撑基板（20）的第二表面直至所述装置结构（40）将（300）通孔（300）从所述第二表面起步，以暴露所述装置结构（40）。 其特征在于，绝缘层的钻孔（300）至少通过湿蚀刻（320）进行。

公开(公告)号：US20140087560A1

公开(公告)日：2014-03-27

申请号：US14009485

申请日：2012-04-18

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： H01L21/288

CPC分类号： H01L21/288 ,  C23C18/32 ,  H01L21/76843 ,  H01L21/76898

摘要： The present invention relates to a kit intended for the deposition of nickel or cobalt in the cavities of a semiconductor substrate intended to form through-silicon vias (TSV) for making interconnections in integrated circuits in three dimensions.The invention also relates to a method of metallization of the insulating surface of such a substrate which comprises contacting the surface with a liquid aqueous solution containing: at least one metal salt of nickel or cobalt; at least one reducing agent; at least one polymer bearing amine functions, and at least one agent stabilizing the metal ions. The step coverage of the layer of nickel or cobalt obtained can be greater than 80%, which facilitates subsequent filling of the vias with copper by electrodeposition.

摘要翻译： 本发明涉及一种用于在半导体衬底的腔中沉积镍或钴的试剂盒，旨在形成用于在三维集成电路中形成互连的通硅通孔（TSV）。 本发明还涉及这种衬底的绝缘表面的金属化方法，其包括使表面与含有至少一种镍或钴的金属盐的液体水溶液接触; 至少一种还原剂; 至少一种带有聚合物的胺起作用，以及至少一种稳定金属离子的试剂。 获得的镍或钴层的阶梯覆盖率可以大于80％，这有利于随后通过电沉积用铜填充通孔。

公开(公告)号：US20100003808A1

公开(公告)日：2010-01-07

申请号：US12495137

申请日：2009-06-30

申请人： Vincent MEVELLEC ,  José GONZALES ,  Dominique SUHR

发明人： Vincent MEVELLEC ,  José GONZALES ,  Dominique SUHR

IPC分类号： H01L21/768 ,  B05D5/12 ,  H01L23/48 ,  H05K1/09

CPC分类号： H01L21/02118 ,  C25D7/123 ,  C25D13/18 ,  H01L21/02282 ,  H01L21/288 ,  H01L21/312 ,  H01L21/76843 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate.According to the invention, this method comprises: a) bringing said surface into contact with a liquid solution comprising: a protic solvent; at least one diazonium salt; at least one monomer that is chain-polymerizable and soluble in said protic solvent; at least one acid in a sufficient quantity to stabilize said diazonium salt by adjusting the pH of said solution to a value less than 7, preferably less than 2.5; b) the polarization of said surface according to a potentio- or galvano-pulsed mode for a duration sufficient to form a film having a thickness of at least 60 nanometres, and preferably between 80 and 500 nanometres. Application: Metallization of through-vias, especially of 3D integrated circuits.

摘要翻译： 本发明基本上涉及在诸如硅衬底的电导体或半导体衬底的表面上制备电绝缘膜的方法。 根据本发明，该方法包括：a）使所述表面与包含质子溶剂的液体溶液接触; 至少一种重氮盐; 至少一种可聚合并可溶于所述质子溶剂的单体; 至少一种足够量的酸以通过将所述溶液的pH调节至小于7，优选小于2.5的值来稳定所述重氮盐; b）根据电位或电流脉冲模式的所述表面的极化持续足够长的时间以形成厚度为至少60纳米，优选为80至500纳米的膜。 应用：通孔的金属化，特别是3D集成电路的金属化。

公开(公告)号：US09190283B2

公开(公告)日：2015-11-17

申请号：US14009485

申请日：2012-04-18

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： H01L21/288 ,  C23C18/32

CPC分类号： H01L21/288 ,  C23C18/32 ,  H01L21/76843 ,  H01L21/76898

摘要： The present invention relates to a kit intended for the deposition of nickel or cobalt in the cavities of a semiconductor substrate intended to form through-silicon vias (TSV) for making interconnections in integrated circuits in three dimensions.The invention also relates to a method of metallization of the insulating surface of such a substrate which comprises contacting the surface with a liquid aqueous solution containing: at least one metal salt of nickel or cobalt; at least one reducing agent; at least one polymer bearing amine functions, and at least one agent stabilizing the metal ions. The step coverage of the layer of nickel or cobalt obtained can be greater than 80%, which facilitates subsequent filling of the vias with copper by electrodeposition.

摘要翻译： 本发明涉及一种用于在半导体衬底的空腔中沉积镍或钴的试剂盒，旨在形成用于在三维集成电路中形成互连的通硅通孔（TSV）。 本发明还涉及这种衬底的绝缘表面的金属化方法，其包括使表面与含有至少一种镍或钴的金属盐的液体水溶液接触; 至少一种还原剂; 至少一种带有聚合物的胺起作用，以及至少一种稳定金属离子的试剂。 获得的镍或钴层的阶梯覆盖率可以大于80％，这有利于随后通过电沉积用铜填充通孔。

公开(公告)号：US08883641B2

公开(公告)日：2014-11-11

申请号：US13393917

申请日：2010-09-30

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： H01L21/44 ,  C23C18/32 ,  C23C18/18 ,  C23C18/16

CPC分类号： C23C18/1882 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1879 ,  C23C18/32 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76898

摘要： The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method.According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.

摘要翻译： 本发明涉及一种用于激活衬底的氧化表面，特别是半导体衬底的氧化表面的方法和方法，用于随后通过由无电镀方法沉积的金属层进行涂覆。 根据本发明，该组合物包含：A）由一种或多种钯络合物组成的活化剂; B）由一种或多种有机硅烷配合物组成的双官能有机粘合剂; C）包含一种或多种用于增溶所述活化剂和所述粘合剂的溶剂的溶剂体系。

公开(公告)号：US20140084474A1

公开(公告)日：2014-03-27

申请号：US14119184

申请日：2012-05-22

申请人： Dominique Suhr ,  Vincent Mevellec

发明人： Dominique Suhr ,  Vincent Mevellec

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L21/76816 ,  H01L21/02063 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/76823 ,  H01L21/76831 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The invention proposes a method for forming a vertical electrical connection (50) in a layered semiconductor structure (1), comprising the following steps: —providing (100) a layered semiconductor structure (1), said layered semiconductor structure (1) comprising: —a support substrate (20) including an first surface (22) and a second surface (24), —an insulating layer (30) overlying the first surface (22) of the support substrate (20), and —at least one device structure (40) formed in the insulating layer (30); and —drilling (300) a via (50) from the second surface of the support substrate (20) up to the device structure (40), in order to expose the device structure (40); characterized in that drilling (300) of the insulating layer is at least performed by wet etching (320).

摘要翻译： 本发明提出了一种在层状半导体结构（1）中形成垂直电连接（50）的方法，包括以下步骤：提供（100）层状半导体结构（1），所述分层半导体结构（1）包括： - 包括第一表面（22）和第二表面（24）的支撑衬底（20）， - 覆盖所述支撑衬底（20）的第一表面（22）的绝缘层（30），以及 - 至少一个器件 在绝缘层（30）中形成的结构（40）; 以及从所述支撑基板（20）的第二表面直至所述装置结构（40）将（300）通孔（300）从所述第二表面起步，以暴露所述装置结构（40）。 其特征在于，绝缘层的钻孔（300）至少通过湿蚀刻（320）进行。

公开(公告)号：US20120196441A1

公开(公告)日：2012-08-02

申请号：US13393917

申请日：2010-09-30

申请人： Vincent Mevellec ,  Dominique Suhr

发明人： Vincent Mevellec ,  Dominique Suhr

IPC分类号： H01L21/3205 ,  H01L21/316 ,  C09D5/00

CPC分类号： C23C18/1882 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1879 ,  C23C18/32 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76898

摘要： The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method.According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.

摘要翻译： 本发明涉及一种用于激活衬底的氧化表面，特别是半导体衬底的氧化表面的方法和方法，用于随后通过由无电镀方法沉积的金属层进行涂覆。 根据本发明，该组合物包含：A）由一种或多种钯络合物组成的活化剂; B）由一种或多种有机硅烷配合物组成的双官能有机粘合剂; C）包含一种或多种用于增溶所述活化剂和所述粘合剂的溶剂的溶剂体系。