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    Method for Manufacturing a Ceramic Electronic Component
    2.
    发明申请
    Method for Manufacturing a Ceramic Electronic Component 失效
    陶瓷电子元件制造方法

    公开(公告)号：US20070245555A1

    公开(公告)日：2007-10-25

    申请号：US11573691

    申请日：2005-09-22

    申请人： Fumio Uchikoba

    发明人： Fumio Uchikoba

    IPC分类号： H01K3/22 ,  H01G7/00

    CPC分类号： H05K3/1258 ,  H01C7/003 ,  H01C17/065 ,  H01F41/041 ,  H01F41/042 ,  H01F41/046 ,  H01G4/005 ,  H01G4/33 ,  H05K1/092 ,  H05K3/207 ,  H05K2203/0264 ,  H05K2203/0568 ,  Y10T29/435 ,  Y10T29/4902 ,  Y10T29/49128 ,  Y10T29/49155

    摘要： A photo-resist 11 of a dry film 10 is patterned to form opening portions 111 and non-opening portions 112 (see FIG. 1(a)). An electrically conductive paste 21 is applied by a doctor blade 31 (see FIG. 1(b)) and thereafter is dried (see FIG. 1(c)). Then, a release film 12 of the dry film 10 is removed (see FIG. 1(d)) and thereafter the dry film 10 is adhered to a ceramic green sheet 41 (see FIG. 1(e)). The photo-resist 11 is removed from the ceramic green sheet 41 to form an electrically conductive film 42 on the ceramic green sheet 41 (see FIG. 1(e)). The ceramic electronic component is manufactured by sintering the ceramic green sheet 41 having the electrically conductive film 41 formed.

    摘要翻译： 对干膜10的光致抗蚀剂11进行图案化，形成开口部111和非开口部112（参照图1（a））。 通过刮刀31（参照图1（b））涂敷导电膏21，然后干燥（参照图1（c））。 然后，除去干膜10的剥离膜12（参照图1（d）），然后将干膜10粘贴在陶瓷生片41上（参照图1（e））。 从陶瓷生片41除去光致抗蚀剂11，在陶瓷生片41上形成导电膜42（参照图1（e））。 通过烧结形成有导电膜41的陶瓷生片41来制造陶瓷电子部件。

    Inductor device
    5.
    发明授权
    Inductor device 有权
    电感器件

    公开(公告)号：US07173508B2

    公开(公告)日：2007-02-06

    申请号：US10862402

    申请日：2004-06-08

    申请人： Toshiyuki Anbo ,  Fumio Uchikoba

    发明人： Toshiyuki Anbo ,  Fumio Uchikoba

    IPC分类号： H01F7/06

    CPC分类号： H01F41/043 ,  H01F17/0013 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49073 ,  Y10T29/49078

    摘要： An inductor device including a device body having a plurality of insulating layers; a plurality of conductive coil pattern units formed inside the device body between insulating layers along a single planar direction, coil pattern units adjoining each other in the single plane being centro-symmetric patterns with respect to a center point of a boundary line between unit sections containing coil pattern units; and connection portions connecting upper and lower coil pattern units separated by the insulating layers to form a coil. It is possible to obtain an inductor device able to suppress the stack deviation without complicating the production process even if the device is made small in size.

    摘要翻译： 一种电感器件，包括具有多个绝缘层的器件主体; 沿着单个平面方向在绝缘层之间在器件本体内部形成的多个导电线圈图案单元，在单个平面中彼此相邻的线圈图案单元相对于包含以下的单元部分之间的边界线的中心点的中心对称图案 线圈图案单位; 以及连接部，其连接由绝缘层分隔开的上下线圈图案单元，以形成线圈。 即使设备尺寸小，也可以获得能够抑制堆叠偏移而不会使生产过程复杂化的电感器件。

    Multi-layer ferrite chip inductor array and manufacturing method thereof
    6.
    发明授权
    Multi-layer ferrite chip inductor array and manufacturing method thereof 有权
    多层铁氧体芯片电感阵列及其制造方法

    公开(公告)号：US06489875B1

    公开(公告)日：2002-12-03

    申请号：US09611212

    申请日：2000-07-06

    申请人： Fumio Uchikoba ,  Tomoyuki Tatemori

    发明人： Fumio Uchikoba ,  Tomoyuki Tatemori

    IPC分类号： H01F500

    CPC分类号： H01F41/041 ,  H01F17/0013 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49128 ,  Y10T29/49155

    摘要： A multi-layer ferrite chip inductor array, wherein an element main body 11 is composed by laminating a ferrite layer and a conductor layer in such a manner that the laminated face thereof is vertical with an element mounting surface 15, a plurality of coil shaped internal conductors are furnished within the element main body 11, the coiling direction of said coil shaped internal conductor being parallel with the element mounting surface, and the ferrite sheets formed with through-holes are printed with a plurality of coil shaped internal conductors and conductor patterns with the electrically conductive material, and the ferrite sheets are laminated such that the laminated face thereof is vertical with the element mounting surface. This realization of the invention depends on the production method having the process enabling to obtain the laminated body where the plurality of coil shaped internal conductors are formed, the coiling direction of said conductors being parallel with said element mounting surface.

    摘要翻译： 一种多层铁氧体芯片电感器阵列，其中元件主体11通过层叠铁氧体层和导体层而构成，使得其层叠面与元件安装表面15垂直，多个线圈形内部 导体配置在元件主体11内，所述线圈状内部导体的卷绕方向与元件安装面平行，并且形成有通孔的铁氧体片被印刷有多个线圈形内部导体和导体图案， 导电材料和铁氧体片层叠，使得其层叠面与元件安装面垂直。 本发明的这种实现取决于具有能够获得形成有多个线圈状内部导体的层叠体的处理的制造方法，所述导体的卷绕方向与所述元件安装面平行。

    Multilayer inductor and production method thereof
    7.
    发明授权
    Multilayer inductor and production method thereof 失效
    多层电感及其制作方法

    公开(公告)号：US06404318B1

    公开(公告)日：2002-06-11

    申请号：US09632213

    申请日：2000-08-03

    申请人： Fumio Uchikoba ,  Noriyuki Kojima

    发明人： Fumio Uchikoba ,  Noriyuki Kojima

    IPC分类号： H01F500

    CPC分类号： H01F27/027 ,  Y10T29/49002 ,  Y10T29/4902 ,  Y10T29/49146 ,  Y10T29/49163

    摘要： In the multilayer inductor, the substrate thereof is composed of a constituent belonging to spinel ferrite, and is furnished with internal conductors of a main constituent being silver at the interior of the substrate. The internal conductors are drawn outside of the substrate, and the drawn portions are provided with external electrodes. The internal conductors contain manganese and bismuth, and the manganese and bismuth contents at an interface between the internal conductors and the substrate are more than those of other ranges. MnO2 of 0.02 to 0.1 wt % and Bi2O3 of 0.5 to 1.2 wt % are added to a paste of the main constituent being silver to be used to the internal conductors, and the paste is baked together with spinel ferrite material.

    摘要翻译： 在多层电感器中，其基板由属于尖晶石型铁氧体的构成构成，并且在基板的内部配备有主要成分为银的内部导体。 内部导体被拉出到基板的外部，并且拉出部分设置有外部电极。 内部导体含有锰和铋，内部导体和基板之间的界面处的锰和铋含量大于其他范围。 将0.02〜0.1重量％的MnO 2和0.5〜1.2重量％的Bi 2 O 3添加到用于内部导体的主要成分为银的糊料中，并将该糊料与尖晶石铁氧体材料一起烘烤。

    Process of manufacturing an inductor device with stacked coil pattern units
    8.
    发明授权
    Process of manufacturing an inductor device with stacked coil pattern units 失效
    制造具有堆叠线圈图案单元的电感器件的工艺

    公开(公告)号：US06345434B1

    公开(公告)日：2002-02-12

    申请号：US09346697

    申请日：1999-07-02

    申请人： Toshiyuki Anbo ,  Fumio Uchikoba

    发明人： Toshiyuki Anbo ,  Fumio Uchikoba

    IPC分类号： H01F706

    CPC分类号： H01F41/043 ,  H01F17/0013 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49073 ,  Y10T29/49078

    摘要： A process for the production of an inductor device comprising the steps of forming a green sheet to form an insulating layer; forming a plurality of conductive coil pattern units on the surface of the green sheet in order that a plurality of unit sections each including a single coil pattern unit are arranged on the surface of the green sheet and each two coil pattern units adjoining in the substantially perpendicular direction to the longitudinal direction of the unit sections are arranged centro-symmetrically with respect to a center point of a boundary line of adjoining unit sections; stacking a plurality of green sheets formed with the plurality of coil pattern units arranged in centro-symmetry and connecting the upper and lower coil pattern units separated by the green sheets to form a coil shape; and sintering the stacked green sheets. It is possible to obtain an inductor device able to suppress the stack deviation without complicating the production process even if the device is made small in size.

    摘要翻译： 一种用于生产电感器件的方法，包括以下步骤：形成生片以形成绝缘层; 在生片的表面上形成多个导电线圈图案单元，以便在生片的表面上布置包括单个线圈图案单元的多个单位部分，并且每个两个线圈图案单元基本垂直地邻接 单元部分的纵向方向相对于相邻单元部分的边界线的中心点中心对称布置; 堆叠形成有多个以中心对称布置的线圈图案单元的多个生片，并连接由生片隔开的上下线圈图案单元以形成线圈形状; 并烧结堆叠的生片。 即使设备尺寸小，也可以获得能够抑制堆叠偏移而不会使生产过程复杂化的电感器件。

    Laminated ferrite chip inductor array
    9.
    发明授权
    Laminated ferrite chip inductor array 有权

    公开(公告)号：US06249206B1

    公开(公告)日：2001-06-19

    申请号：US09460420

    申请日：1999-12-14

    申请人： Fumio Uchikoba ,  Toshiyuki Anbo

    发明人： Fumio Uchikoba ,  Toshiyuki Anbo

    IPC分类号： H01F500

    CPC分类号： H01F17/0013 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49078 ,  Y10T29/49155

    摘要： A laminated ferrite chip inductor array wherein the array is composed in that multiple layers of ferrite sheets printed with U-shaped patterns of internal conductors are piled in such a manner that the U-shaped patterns of the internal conductors on adjacent sheets are opposed one another, and a plurality of channels composed by sintering the piled layers of coil-shaped structure of the internal conductive printed patterns made electrically communicating via through holes pierced in the ferrite sheets are held in ferrite porcelains, characterized in that the internal conductive pattern shapes of the adjacent chip inductors are turned 180 degree one another.