公开(公告)号：US08288275B2

公开(公告)日：2012-10-16

申请号：US12271220

申请日：2008-11-14

Applicant: Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

Inventor： Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/7684 ,  H01L21/76862

Abstract: Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H2 remote plasma treating the W/WN barrier layer, forming a W-plug on the H2 remote plasma treated W/WN barrier layer to fill the contact hole, and chemical mechanical polishing (CMP) the W-plug and then the W/WN barrier layer in order to expose the interlayer insulating layer.

Abstract translation: 提供了形成半导体器件的接触插塞的方法。 形成半导体器件的接触插塞的方法可以包括在其上形成下部结构的半导体衬底上形成层间绝缘层，在层间绝缘层中形成接触孔，暴露下部结构的接触孔，并形成 W层，然后形成WN层，以在接触孔中形成W / WN阻挡层。 方法可以包括H2远程等离子体处理W / WN阻挡层，在H2远程等离子体处理的W / WN阻挡层上形成W-塞以填充接触孔，以及化学机械抛光（CMP）W-塞，然后 W / WN阻挡层，以露出层间绝缘层。

公开(公告)号：US20120150330A1

公开(公告)日：2012-06-14

申请号：US13241575

申请日：2011-09-23

Applicant: Ho-Ki LEE ,  Kye-hyun Baek ,  Young-chuel Lee ,  Gyung-jin Min

Inventor： Ho-Ki LEE ,  Kye-hyun Baek ,  Young-chuel Lee ,  Gyung-jin Min

IPC: G05B13/04

CPC classification number: G05B21/00 ,  G05B19/41875 ,  G05B2219/32187 ,  G05B2219/32191 ,  G05B2219/35346 ,  G05B2219/45031 ,  H01L21/67253 ,  Y02P90/22 ,  Y02P90/86

Abstract: A method of controlling process distribution of a semiconductor process includes receiving process distribution data representing the process distribution of the semiconductor process, receiving a parameter related to the process distribution, generating a virtual metrology model corresponding to the process distribution based on a relationship between the process distribution data and the parameter, and modifying a process variable affecting the process distribution based on the virtual metrology model.

Abstract translation: 一种控制半导体工艺过程分布的方法包括：接收表示半导体处理过程分布的处理分布数据，接收与该过程分布相关的参数，根据该过程之间的关系生成与该过程分布相对应的虚拟度量模型 分布数据和参数，以及基于虚拟计量模型修改影响流程分配的流程变量。

公开(公告)号：US20100166945A1

公开(公告)日：2010-07-01

申请号：US12654721

申请日：2009-12-30

Applicant: Ho-Ki Lee ,  Sung-Ho Han ,  Yong-Jin Kim

Inventor： Ho-Ki Lee ,  Sung-Ho Han ,  Yong-Jin Kim

IPC: C23C14/54 ,  C23C16/513

CPC classification number: C23C16/52

Abstract: A method of calculating a thickness of a layer may include forming the layer on a substrate in a chamber, measuring optical emission spectrum data from the chamber, and calculating the thickness of the layer from the optical emission spectrum data. A method of forming a layer may include depositing the layer on a substrate in a chamber, measuring optical emission spectrum data from the chamber, calculating a thickness of the layer using the optical emission spectrum data, and ending the depositing of the layer when the calculated thickness of the layer is within a target thickness range.

Abstract translation: 计算层的厚度的方法可以包括在室中的基板上形成层，测量来自室的光发射光谱数据，以及根据光发射光谱数据计算层的厚度。 形成层的方法可以包括将层沉积在室中的衬底上，从腔室测量光发射光谱数据，使用光发射光谱数据计算层的厚度，并且当所计算的 该层的厚度在目标厚度范围内。

公开(公告)号：US07662716B2

公开(公告)日：2010-02-16

申请号：US11355112

申请日：2006-02-14

Applicant: Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

Inventor： Hyun-Su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

IPC: H01L21/28 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76855 ,  H01L21/28556 ,  H01L21/76843

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Abstract translation: 可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。 可以在衬底的第一器件区域上的介电层中形成第一接触孔。 然后可以在第一接触孔中形成硅化物层。 可以在形成第一接触孔和硅化物层之后形成第二接触孔。 然后可以在第一和第二接触孔中执行第二硅化。

公开(公告)号：US20080296660A1

公开(公告)日：2008-12-04

申请号：US11947006

申请日：2007-11-29

Applicant: Jinho PARK ,  Sang-Woo LEE ,  Ho-Ki LEE ,  Gilheyun CHOI

Inventor： Jinho PARK ,  Sang-Woo LEE ,  Ho-Ki LEE ,  Gilheyun CHOI

IPC: H01L29/00 ,  C23C16/00 ,  B32B7/02

CPC classification number: H01L21/28061 ,  H01L21/28556 ,  H01L21/67207 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/4925 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T428/24942 ,  H01L2924/00

Abstract: A conductive structure and method for making same is disclosed and includes a first nucleation layer formed by performing a cyclic deposition process on a substrate, a second nucleation layer formed on the first nucleation layer by a CVD process, and a bulk metal layer formed on the second nucleation layer.

Abstract translation: 公开了导电结构及其制造方法，包括通过在基板上进行循环沉积工艺而形成的第一成核层，通过CVD工艺在第一成核层上形成的第二成核层和形成在第一成核层上的体金属层 第二成核层。

公开(公告)号：US20080214012A1

公开(公告)日：2008-09-04

申请号：US12007517

申请日：2008-01-11

Applicant: Jin-ho Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

Inventor： Jin-ho Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

IPC: H01L21/302 ,  C23C16/455

CPC classification number: C23C16/45519 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4557

Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.

Abstract translation: 用于制造半导体器件的装置和方法可以通过减少微粒的产生和减少清洗次数来提高操作效率来增加半导体器件的可靠性。 该装置可以包括具有盖板的室，用于将半导体衬底牢固地放置在室内的基座，位于盖板上的喷淋头以将反应气体供应到室中，以及连接到盖板以提供加热帘幕的帘式气体管线 淋浴头之间的气体。

公开(公告)号：US20080136040A1

公开(公告)日：2008-06-12

申请号：US11778344

申请日：2007-07-16

Applicant: Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

Inventor： Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein. An electrically conductive pattern is formed in the opening. A second metal nitride layer is provided between the electrically conductive pattern and the nitrified first metal layer.

Abstract translation: 形成电互连的方法包括：在半导体衬底上形成第一电绝缘层，然后在第一电绝缘层中形成开口。 进行步骤以使开口的侧壁与其中具有不均匀氮浓度的硝化的第一金属层一起排列。 在开口中形成导电图案。 第二金属氮化物层设置在导电图案和硝化的第一金属层之间。

公开(公告)号：US09464539B2

公开(公告)日：2016-10-11

申请号：US14364655

申请日：2011-12-06

Applicant: Moon Ho Son ,  Gun Il Park ,  Sung Jae Lee ,  Ho Ki Lee ,  Jung Kun Jin ,  Jae Woong Choi

Inventor： Moon Ho Son ,  Gun Il Park ,  Sung Jae Lee ,  Ho Ki Lee ,  Jung Kun Jin ,  Jae Woong Choi

IPC: F01K15/04 ,  F01K23/06 ,  F01K25/08 ,  F01K27/02 ,  F01K23/10

CPC classification number: F01K15/04 ,  F01K23/065 ,  F01K23/10 ,  F01K25/08 ,  F01K27/02

Abstract: A waste heat recovery device for a marine vessel is disclosed. According to the embodiments of the present invention, the waste heat recovery device for a marine vessel includes: a heat exchanger, which recovers heat from the exhaust fumes discharged from the engine, to heat a first refrigerant under uniform pressure; a turbine which is driven by adiabatically expanding the first refrigerant heated under uniform pressure; a condenser which condenses the adiabatically expanded first refrigerant; and a heat exchanging pump which compresses the condensed first refrigerant so as to re-circulate the compressed first refrigerant to the heat exchanger.

Abstract translation: 公开了一种用于船舶的废热回收装置。 根据本发明的实施例，用于船舶的废热回收装置包括：热交换器，其从发动机排出的废气中回收热量，以在均匀的压力下加热第一制冷剂; 涡轮机，其通过绝热膨胀在均匀压力下加热的第一制冷剂驱动; 冷凝器，其将绝热膨胀的第一制冷剂冷凝; 以及热交换泵，其压缩冷凝的第一制冷剂，以将压缩的第一制冷剂再循环到热交换器。

公开(公告)号：US20120216954A1

公开(公告)日：2012-08-30

申请号：US13459275

申请日：2012-04-30

Applicant: Jin-ho PARK ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

Inventor： Jin-ho PARK ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

IPC: H01L21/306 ,  C23C16/455

CPC classification number: C23C16/45519 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4557

Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.

Abstract translation: 用于制造半导体器件的装置和方法可以通过减少微粒的产生和减少清洗次数来提高操作效率来增加半导体器件的可靠性。 该装置可以包括具有盖板的室，用于将半导体衬底牢固地放置在室内的基座，位于盖板上的喷淋头以将反应气体供应到室中，以及连接到盖板以提供加热帘幕的帘式气体管线 淋浴头之间的气体。

公开(公告)号：US20120012969A1

公开(公告)日：2012-01-19

申请号：US13240599

申请日：2011-09-22

Applicant: Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

Inventor： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC: H01L27/108

CPC classification number: H01L23/485 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76865 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract translation: 在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。 绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。 绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。 在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。 因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。