公开(公告)号：US10043817B2

公开(公告)日：2018-08-07

申请号：US15212356

申请日：2016-07-18

申请人： Tae-Hee Lee ,  Hong-Soo Kim ,  Kyoung-Hoon Kim ,  Young-Suk Lee

发明人： Tae-Hee Lee ,  Hong-Soo Kim ,  Kyoung-Hoon Kim ,  Young-Suk Lee

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  G11C16/08 ,  H01L27/11568 ,  H01L27/11573 ,  G11C16/04

摘要： A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

公开(公告)号：US20170301684A1

公开(公告)日：2017-10-19

申请号：US15490154

申请日：2017-04-18

申请人： Jong-kook PARK ,  Hong-soo Kim ,  Tae-keun Cho

发明人： Jong-kook PARK ,  Hong-soo Kim ,  Tae-keun Cho

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region.

公开(公告)号：US20140203442A1

公开(公告)日：2014-07-24

申请号：US14157830

申请日：2014-01-17

申请人： Jang-Gn Yun ,  Hong-Soo Kim ,  Hoo-Sung Cho

发明人： Jang-Gn Yun ,  Hong-Soo Kim ,  Hoo-Sung Cho

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

摘要翻译： 提供三维半导体器件的接线结构及其形成方法。 布线结构可以包括上字线和下字线，每个字线在纵向方向上延伸。 上字线可以包括在横向方向上仅延伸上部字线的一部分的凹部，下部字线可以包括由上部字线的凹部露出的布线区域。 布线结构还可以包括接触上部字线的上部接触插塞和与接线区域接触的下部接触插头。 上下接触塞可以在垂直方向上延伸。

公开(公告)号：US08772852B2

公开(公告)日：2014-07-08

申请号：US12328141

申请日：2008-12-04

申请人： Hong-Soo Kim ,  Keon-Soo Kim

发明人： Hong-Soo Kim ,  Keon-Soo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/7881

摘要： Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.

摘要翻译： 提供了包括公共源的非易失性存储器件。 该器件包括与第二有源区域交叉的第一有源区，设置在第二有源区中的公共源，以及平行于公共源设置在公共源上的源极导线。 源极导线与公共源电连接。

公开(公告)号：US08139413B2

公开(公告)日：2012-03-20

申请号：US12367889

申请日：2009-02-09

申请人： Hong-Soo Kim ,  Hwa-Kyung Shin ,  Min-Chul Kim

发明人： Hong-Soo Kim ,  Hwa-Kyung Shin ,  Min-Chul Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and define memory block pairs. The flash memory device can further include a row selection circuit that is configured to drive the word lines responsive to memory operations associated with a memory address, where the row selection circuit can include respective shield lines that are located between the memory blocks included in each pair and each of the memory blocks in the pair has a common source line therebetween.

摘要翻译： 闪速存储器件可以包括存储单元阵列，其包括多个存储器块，其中每个存储器块具有排列在字线和位线的交点处的存储器单元，其中多个存储器块中的一个存储器块紧邻于一个 另一个并定义内存块对。 闪存器件还可以包括行选择电路，其被配置为响应于与存储器地址相关联的存储器操作来驱动字线，其中行选择电路可以包括位于每对中包括的存储器块之间的各个屏蔽线 并且该对中的每个存储器块之间具有公共源极线。

公开(公告)号：US20120028435A1

公开(公告)日：2012-02-02

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US20120009120A1

公开(公告)日：2012-01-12

申请号：US12843159

申请日：2010-07-26

申请人： CHURL-HEE CHO ,  Jeong-Gu Yeo ,  Young-Soo Ahn ,  Si-Kyung Kim ,  Joon-Soo Kim ,  Nam-Jo Jeong ,  Bo-Yun Jang ,  Dong-Kook Kim ,  Hong-Soo Kim

发明人： CHURL-HEE CHO ,  Jeong-Gu Yeo ,  Young-Soo Ahn ,  Si-Kyung Kim ,  Joon-Soo Kim ,  Nam-Jo Jeong ,  Bo-Yun Jang ,  Dong-Kook Kim ,  Hong-Soo Kim

IPC分类号： C01B39/02

CPC分类号： B01D71/028 ,  B01D67/0051 ,  B01D69/10 ,  B01D2323/46

摘要： The present disclosure relates to a thermal cracking resistant zeolite membrane and a method of fabricating the same. The method includes dissolving an alumina-based material, a silica-based material and sodium hydroxide in water to prepare an aqueous solution, stirring the aqueous solution to form a hydrothermal solution, preparing a slurry of zeolite seeds through wet-type vibration pulverization and centrifugal separation of zeolite powder, passing the zeolite seeds through a support by vacuum filtration such that the zeolite seeds can be infiltrated into an inner region of the support ranging from a depth of 3 μm to a depth corresponding to 50% of a total thickness of the support, and immersing the support into the hydrothermal solution for hydrothermal treatment to grow a dense zeolite separation layer not only on the surface of the support but also on the inner region thereof. The zeolite membrane prevents the occurrence of thermal cracking on the zeolite separation layer, thereby providing good thermal stability and separation performance during heating and at a target processing temperature.

摘要翻译： 本发明涉及耐热裂解沸石膜及其制造方法。 该方法包括将氧化铝基材料，二氧化硅基材料和氢氧化钠溶解在水中以制备水溶液，搅拌该水溶液以形成水热溶液，通过湿式振动粉碎和离心制备沸石种子的浆料 分离沸石粉末，通过真空过滤将沸石种子通过支持物，使得沸石种子可以渗透到载体的内部区域中，范围从3μm的深度到相当于总厚度的50％的深度 支撑并将载体浸入用于水热处理的水热溶液中，不仅在支撑体的表面上而且在其内部区域上生长致密的沸石分离层。 沸石膜防止沸石分离层发生热裂解，从而在加热和目标加工温度下提供良好的热稳定性和分离性能。

公开(公告)号：US20110303965A1

公开(公告)日：2011-12-15

申请号：US13099482

申请日：2011-05-03

申请人： Hong-Soo Kim ,  Hwa-Kyung Shin ,  Moo-Kyung Lee ,  Jong-Ho Lim

发明人： Hong-Soo Kim ,  Hwa-Kyung Shin ,  Moo-Kyung Lee ,  Jong-Ho Lim

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7881

摘要： A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

摘要翻译： 半导体器件和半导体器件的制造方法包括在衬底上形成的多个第一有源区和第二有源区。 第二有源区形成在两个第一有源区之间。 在相应的第一有源区上形成多个栅极结构。 在第二有源区上形成虚拟栅极结构，并将第一电压施加到虚拟栅极结构。

公开(公告)号：US20110196915A1

公开(公告)日：2011-08-11

申请号：US12912425

申请日：2010-10-26

申请人： Hong-soo KIM ,  Jong-ho LEE ,  Do-jun YANG ,  Tae-jeoung KIM ,  Min-kyoung KANG

发明人： Hong-soo KIM ,  Jong-ho LEE ,  Do-jun YANG ,  Tae-jeoung KIM ,  Min-kyoung KANG

IPC分类号： G06F15/16

CPC分类号： H04L12/2805 ,  H04L12/2818 ,  H04L2012/2849

摘要： A method and apparatus for using a service provided by a universal plug and play (UPnP) device of a home network, based on a user interface (UI) received by a client located outside of the home network from a server for managing at least one UI for a remote access.

摘要翻译： 一种用于使用由家庭网络的通用即插即用（UPnP）设备提供的服务的方法和装置，其基于由位于家庭网络外部的客户端从服务器接收的用户界面（UI），用于管理至少一个 用于远程访问的UI。

公开(公告)号：US20110159221A1

公开(公告)日：2011-06-30

申请号：US12878900

申请日：2010-09-09

申请人： Churl-Hee CHO ,  Do-Kyung KIM ,  Jeong-Gu YEO ,  Young-Soo Ahn ,  Dong-Kook KIM ,  Hong-Soo KIM

发明人： Churl-Hee CHO ,  Do-Kyung KIM ,  Jeong-Gu YEO ,  Young-Soo Ahn ,  Dong-Kook KIM ,  Hong-Soo KIM

IPC分类号： D02G3/02 ,  C08L81/06 ,  C08L33/20 ,  C08L27/16 ,  C08L33/24 ,  C08L1/12 ,  D02G1/00

CPC分类号： B29C47/0026 ,  B01D69/08 ,  B01D69/087 ,  B01D71/024 ,  B22F3/23 ,  B82Y30/00 ,  C04B35/62236 ,  C04B35/62272 ,  C04B35/62281 ,  C04B35/62295 ,  C04B35/634 ,  C04B2235/404 ,  C04B2235/421 ,  C04B2235/5284 ,  C09D5/00 ,  C22C1/058 ,  C22C29/00 ,  C22C29/02 ,  C22C29/12 ,  C22C29/16 ,  C22C47/14 ,  D01D10/02 ,  D01F9/08 ,  Y10T428/1369

摘要： Disclosed herein is a method of manufacturing inorganic hollow yarns, such as cermets, oxide-non oxide composites, poorly sinterable non-oxides, and the like, at low costs. The method includes preparing a composition comprising a self-propagating high temperature reactant, a polymer and a dispersant, wet-spinning the composition through a spinneret to form wet-spun yarns, washing and drying the wet-spun yarns to form polymer-self propagating high temperature reactant hollow yarns, and heat-treating the polymer-self propagating high temperature reactant hollow yarns to remove a polymeric component from the polymer-self propagating high temperature reactant hollow yarns while inducing self-propagating high temperature reaction of the self-propagating high temperature reactant to form inorganic hollow yarns. The composition comprises 45˜60 wt % of the self-propagating high temperature reactant, 6˜17 wt % of the polymer, 0.1˜4 wt % of the dispersant, and the balance of an organic solvent.

摘要翻译： 本文公开了以低成本制造无机中空丝的方法，例如金属陶瓷，氧化物非氧化物复合材料，不易烧结的非氧化物等。 该方法包括制备包含自蔓延高温反应物，聚合物和分散剂的组合物，通过喷丝头将组合物湿纺以形成湿纺丝，洗涤和干燥湿纺丝以形成聚合物自传播 高温反应物中空纱线，并热处理聚合物自蔓延高温反应物中空纱线，以从聚合物自传播的高温反应物中空纱线中除去聚合物组分，同时诱导自传播高自由度的高温反应 温度反应物形成无机中空纱线。 组合物包含45〜60重量％的自蔓延高温反应物，6〜17重量％的聚合物，0.1〜4重量％的分散剂和余量的有机溶剂。