公开(公告)号：US20160293618A1

公开(公告)日：2016-10-06

申请号：US15015116

申请日：2016-02-03

Applicant: Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

Inventor： Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423 ,  H01L29/792 ,  H01L29/49

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract translation: 半导体器件包括衬底，衬底上的隧道绝缘图案，隧道绝缘图案上的电荷存储图案，具有小于电荷存储图案上的电荷存储图案的宽度的电介质图案，具有 大于电介质图案上的电介质图案的宽度的宽度，以及控制栅上的含金属栅极。

公开(公告)号：US20160343729A1

公开(公告)日：2016-11-24

申请号：US15142365

申请日：2016-04-29

Applicant: Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

Inventor： Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成结构，所述结构包括金属图案，所述金属图案的至少一部分被暴露; 形成预备的缓冲氧化物层以覆盖该结构，金属氧化物层形成在金属图案的暴露部分; 并且使金属氧化物层脱氧，使得预备缓冲氧化物层转变成缓冲氧化物层。

公开(公告)号：US20170278936A1

公开(公告)日：2017-09-28

申请号：US15604646

申请日：2017-05-24

Applicant: Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

Inventor： Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

IPC: H01L29/423 ,  H01L27/11519 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US09698231B2

公开(公告)日：2017-07-04

申请号：US15015116

申请日：2016-02-03

Applicant: Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

Inventor： Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US20160122871A1

公开(公告)日：2016-05-05

申请号：US14743101

申请日：2015-06-18

Applicant: Sang Hoon Lee ,  Jin Gyun Kim ,  Hyun Jin Shin ,  Han Vit Yang ,  Yong Seok Cho

Inventor： Sang Hoon Lee ,  Jin Gyun Kim ,  Hyun Jin Shin ,  Han Vit Yang ,  Yong Seok Cho

IPC: C23C16/455 ,  C23C16/50 ,  H01J37/32 ,  C23C16/52

CPC classification number: H01J37/32449 ,  C23C16/045 ,  C23C16/452 ,  C23C16/45536 ,  H01J37/321 ,  H01L27/11582 ,  H01L29/40117

Abstract: An atomic layer deposition (ALD) apparatus includes a first process chamber in which a substrate is accommodated, a plasma generating unit provided on the outside of the first process chamber, a source gas supply unit provided on an upper portion of the plasma generating unit, and configured to supply a plurality of source gases, a purge gas supply unit configured to supply a purge gas to the first process chamber, and a gas control unit configured to control the supply of the source gases and the purge gas, wherein the plasma generating unit includes a second process chamber providing a space in which plasma is generated and a plasma antenna inducing a magnetic field in the second process chamber, and the source gases are supplied to the first process chamber through the plasma generating unit.

Abstract translation: 原子层沉积（ALD）装置包括容纳基板的第一处理室，设置在第一处理室外侧的等离子体产生单元，设置在等离子体产生单元的上部的源气体供应单元， 并且被配置为提供多个源气体;净化气体供应单元，被配置为向第一处理室供应净化气体;气体控制单元，被配置为控制源气体和净化气体的供应，其中等离子体产生 单元包括提供产生等离子体的空间的第二处理室和在第二处理室中产生磁场的等离子体天线，并且源气体通过等离子体产生单元供应到第一处理室。