Semiconductor device and fabrication method
    2.
    发明授权
    Semiconductor device and fabrication method 有权
    半导体器件及其制造方法

    公开(公告)号:US08252671B2

    公开(公告)日:2012-08-28

    申请号:US13186470

    申请日:2011-07-20

    IPC分类号: H01L21/425

    摘要: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

    摘要翻译: 一个实施例中的半导体器件具有布置在第一和第二连接区域之间的第一连接区域,第二连接区域和半导体体积。 在第二连接区域的附近,在半导体体积中形成空间电荷区域的场停止区域以及与第一连接区域相邻的阳极区域在半导体体积内设置。 半导体体积内的掺杂剂浓度分布被配置为使得从第二连接区域的面对第二连接区域的阳极区域的界面开始,离子化掺杂剂在半导体体积上的电荷积分到达第二连接区域的方向 与半导体器件的击穿电荷相对应的电荷量仅在靠近第二连接区域的场停止区的界面附近。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A FIELD STOP ZONE AT A SPECIFIC DEPTH
    3.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A FIELD STOP ZONE AT A SPECIFIC DEPTH 有权
    在特定深度制造包含现场停止区的半导体器件的方法

    公开(公告)号:US20080124902A1

    公开(公告)日:2008-05-29

    申请号:US11468372

    申请日:2006-08-30

    IPC分类号: H01L21/265

    CPC分类号: H01L21/26586 H01L29/66333

    摘要: Some embodiments of the invention relate to manufacturing a semiconductor device with an implantation layer on a semiconductor substrate including a method of manufacturing such an implantation layer, wherein said implantation layer is formed in an implantation step at a predetermined depth of penetration, determined from a top surface of said semiconductor substrate, using a particle beam, by increasing its path distance to a main implantation peak and correspondingly increasing the energy level of said particle beam for producing an undamaged implantation layer having a thickness that is increased significantly compared with the thickness of an implantation layer that would be produced at said predetermined depth of penetration using a particle beam with non-increased path distance and energy level.

    摘要翻译: 本发明的一些实施例涉及在半导体衬底上制造具有注入层的半导体器件,该半导体器件包括制造这种注入层的方法,其中所述注入层以从顶部确定的预定穿透深度的注入步骤形成 所述半导体衬底的表面使用粒子束,通过增加其到主注入峰的路径距离并相应地增加所述粒子束的能级,用于产生未损坏的注入层,其具有与其厚度相比显着增加的厚度 使用具有非增加的路径距离和能级的粒子束在所述预定的穿透深度下产生的植入层。

    Method for manufacturing a semiconductor substrate including laser annealing
    4.
    发明授权
    Method for manufacturing a semiconductor substrate including laser annealing 有权
    包括激光退火的半导体衬底的制造方法

    公开(公告)号:US07842590B2

    公开(公告)日:2010-11-30

    申请号:US12110740

    申请日:2008-04-28

    IPC分类号: H01L21/425

    摘要: A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the semiconductor substrate at the second surface such that its peak doping concentration in the semiconductor substrate is located at a first depth with respect to the second surface. A second dopant is introduced into the semiconductor surface at the second surface such that its peak doping concentration in the semiconductor substrate is located at a second depth with respect to the second surface, wherein the first depth is larger than the second depth. At least a first laser anneal is performed by directing at least one laser beam pulse onto the second surface to melt the semiconductor substrate, at least in sections, at the second surface.

    摘要翻译: 一种通过激光退火制造半导体器件的方法。 一个实施例提供了具有第一表面和第二表面的半导体衬底。 第二表面布置成与第一表面相对。 第一掺杂剂在第二表面被引入半导体衬底中,使得其半导体衬底中的峰值掺杂浓度位于相对于第二表面的第一深度。 第二掺杂剂在第二表面被引入到半导体表面中,使得其半导体衬底中的峰值掺杂浓度相对于第二表面位于第二深度,其中第一深度大于第二深度。 至少通过将至少一个激光束脉冲引导到第二表面上来进行至少第一激光退火,以至少在第二表面上以部分熔化半导体衬底。

    Method for optimizing a controlled system parameter
    5.
    发明授权
    Method for optimizing a controlled system parameter 失效
    优化受控系统参数的方法

    公开(公告)号:US3996452A

    公开(公告)日:1976-12-07

    申请号:US606428

    申请日:1975-08-21

    摘要: A controlled system parameter is optimized by providing at periodic time intervals discrete adjustment steps derived from the difference, with alternating sign, between a constant component and a component which depends on the change of the control system parameter caused by the preceding adjustment step. An application of the method to a ball mill in a cement plant for optimizing its efficiency is shown.

    摘要翻译: 通过在周期性时间间隔提供离散的调整步骤来优化受控系统参数,所述离散调整步骤根据由先前调整步骤引起的控制系统参数的变化的恒定分量和分量之间的差异的交替符号导出。 显示了将该方法应用于水泥厂的球磨机以优化其效率。

    Detecting analytes
    6.
    发明授权
    Detecting analytes 有权
    检测分析物

    公开(公告)号:US08778157B2

    公开(公告)日:2014-07-15

    申请号:US12921902

    申请日:2009-03-11

    IPC分类号: G01N27/447 G01N27/327

    摘要: Provided is a method for processing a sample, which method comprises: a) contacting a binding phase, which binding phase is capable of binding an analyte, with the sample in the presence of a medium; b) applying across the medium a first alternating field composed of a plurality of pulses and having a first frequency, a first pulse duration and a first pulse rise time; c) optionally applying across the medium a second alternating field; and d) thereby influencing the sample and/or the binding phase in the medium.

    摘要翻译: 提供了一种处理样品的方法,该方法包括:a)在介质存在下使结合相与结合相结合,该结合相能够与分析物结合; b)在介质上施加由多个脉冲组成的具有第一频率,第一脉冲持续时间和第一脉冲上升时间的第一交变场; c)任选地在所述介质上施加第二交变场; 和d)从而影响培养基中的样品和/或结合相。

    Method for fabricating a semiconductor having a graded pn junction
    7.
    发明授权
    Method for fabricating a semiconductor having a graded pn junction 有权
    具有渐变pn结的半导体的制造方法

    公开(公告)号:US08741750B2

    公开(公告)日:2014-06-03

    申请号:US12571037

    申请日:2009-09-30

    IPC分类号: H01L21/26

    摘要: A method for fabricating a semiconductor body is presented. The semiconductor body includes a p-conducting zone, an n-conducting zone and a pn junction in a depth T1 in the semiconductor body between the p-conducting zone and the n-conducting zone. The method includes providing the semiconductor body, producing the p-doped zone by the diffusion of an impurity that forms an acceptor in a first direction into the semiconductor body, and producing the n-conducting zone by the implantation of protons in the first direction into the semiconductor body into a depth T2>T1 and the subsequent heat treatment of the semiconductor body in order to form hydrogen-induced donors.

    摘要翻译: 本发明提供一种制造半导体器件的方法。 半导体本体在p导电区和n导电区之间包括在半导体本体中的深度T1的p导电区,n导电区和pn结。 该方法包括提供半导体本体,通过在第一方向上将形成受主的杂质扩散到半导体本体中而产生p掺杂区,并通过沿第一方向注入质子来产生n导电区, 半导体本体进入深度T2> T1并随后对半导体主体进行热处理,以形成氢诱导的供体。

    Semiconductor Device with Trench Structures
    8.
    发明申请
    Semiconductor Device with Trench Structures 有权
    具有沟槽结构的半导体器件

    公开(公告)号:US20130320487A1

    公开(公告)日:2013-12-05

    申请号:US13487540

    申请日:2012-06-04

    IPC分类号: H01L29/06 H01L21/762

    摘要: A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones.

    摘要翻译: 半导体器件的半导体本体包括第一导电类型的掺杂层和第二导电类型的一个或多个掺杂区。 一个或多个掺杂区形成在半导体本体的掺杂层和第一表面之间。 沟槽结构从第一和第二相对表面之一延伸到半导体本体中。 沟槽结构布置在彼此电连接的半导体本体的部分之间。 沟槽结构可以被布置用于减轻机械应力,局部地控制电荷载流子迁移率,局部地控制电荷载流子复合速率和/或成形掩埋扩散区。

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
    半导体器件和制造方法

    公开(公告)号:US20120315747A1

    公开(公告)日:2012-12-13

    申请号:US13558467

    申请日:2012-07-26

    IPC分类号: H01L21/425

    摘要: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

    摘要翻译: 一个实施例中的半导体器件具有布置在第一和第二连接区域之间的第一连接区域,第二连接区域和半导体体积。 在第二连接区域的附近,在半导体体积中形成空间电荷区域的场停止区域以及与第一连接区域相邻的阳极区域在半导体体积内设置。 半导体体积内的掺杂剂浓度分布被配置为使得从第二连接区域的面对第二连接区域的阳极区域的界面开始,离子化掺杂剂在半导体体积上的电荷积分到达第二连接区域的方向 与半导体器件的击穿电荷相对应的电荷量仅在靠近第二连接区域的场停止区的界面附近。

    Semiconductor device and fabrication method
    10.
    发明授权
    Semiconductor device and fabrication method 有权
    半导体器件及其制造方法

    公开(公告)号:US08003502B2

    公开(公告)日:2011-08-23

    申请号:US12416935

    申请日:2009-04-02

    IPC分类号: H01L21/425

    摘要: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

    摘要翻译: 一个实施例中的半导体器件具有布置在第一和第二连接区域之间的第一连接区域,第二连接区域和半导体体积。 在第二连接区域的附近,在半导体体积中形成空间电荷区域的场停止区域以及与第一连接区域相邻的阳极区域在半导体体积内设置。 半导体体积内的掺杂剂浓度分布被配置为使得从第二连接区域的面对第二连接区域的阳极区域的界面开始,离子化掺杂剂在半导体体积上的电荷积分到达第二连接区域的方向 与半导体器件的击穿电荷相对应的电荷量仅在靠近第二连接区域的场停止区的界面附近。