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    Dynamic random access memory having sequential word line refresh
    1.
    发明授权
    Dynamic random access memory having sequential word line refresh 失效
    具有顺序字线刷新的动态随机存取存储器

    公开(公告)号：US5715206A

    公开(公告)日：1998-02-03

    申请号：US701672

    申请日：1996-08-22

    Applicant: Jae-Hyeong Lee ,  Hyung-Kyu Lim

    Inventor： Jae-Hyeong Lee ,  Hyung-Kyu Lim

    IPC: G11C11/34 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

    CPC classification number: G11C11/406

    Abstract: A DRAM includes a refresh controller including a clock control section for producing a refresh mode signal in response to an external control clock signal, a refresh logic section for producing an enable signal in response to the refresh mode signal, a refresh counter for sequentially producing a first plurality of row address signals during an active period of a row address strobe signal in response to the enable signal, a row address buffer for producing a second plurality of row address signals in response to the row address signals, and a row decoder including a plurality of word line drivers which sequentially decode the second plurality of row address signals provided from the row address buffer and sequentially enables word lines corresponding to the decoded row address signals.

    Abstract translation: DRAM包括刷新控制器，该刷新控制器包括响应于外部控制时钟信号产生刷新模式信号的时钟控制部分，用于响应于刷新模式信号产生使能信号的刷新逻辑部分，用于依次产生一个刷新计数器 响应于使能信号在行地址选通信号的有效周期期间的第一多个行地址信号，用于响应于行地址信号产生第二多个行地址信号的行地址缓冲器，以及包括 多个字线驱动器，其顺序地解码从行地址缓冲器提供的第二多行行地址信号，并且顺序地启用与解码的行地址信号相对应的字线。

    Tristate data output buffer having reduced switching noise and intermediate-level setting
    2.
    发明授权
    Tristate data output buffer having reduced switching noise and intermediate-level setting 失效
    三态数据输出缓冲器具有降低的开关噪声和中间级设置

    公开(公告)号：US5311076A

    公开(公告)日：1994-05-10

    申请号：US964622

    申请日：1992-10-23

    Applicant: Yong-Bo Park ,  Hee-Choul Park ,  Hyung-Kyu Lim

    Inventor： Yong-Bo Park ,  Hee-Choul Park ,  Hyung-Kyu Lim

    IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/003

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/0013 ,  H03K19/01728

    Abstract: A data output buffer suitable for use in a semiconductor memory device includes a first input circuit coupled to a first data signal and a first control signal, e.g., an output enable signal, and a second input circuit coupled to a second data signal which is the inverse of the first data signal and the first control signal. The data output buffer also includes a pull-up circuit responsive to the output of the first input circuit for selectively raising the data output node to a high voltage level, e.g., Vcc, and a pull-down circuit responsive to the output of the second input circuit for selectively lowering the data output node to a low voltage level, e.g., Vss. The data output buffer further includes a preset circuit comprised of a first preset control circuit responsive to the output of the first input circuit and a second control signal, e.g., an inverse output enable signal, for selectively raising the data output node from the low voltage level to an intermediate voltage level, e.g., 1/2 Vcc, and a second preset control circuit responsive to the output of the second input circuit and the second control signal for selectively lowering the data output node from the high voltage level to the intermediate voltage level. The preset control circuit advantageously operates to maintain the data output node at the intermediate voltage level during active states of the output enable signal without generating any DC current, thereby eliminating the noise and reliability problems of presently available data output buffers.

    Abstract translation: 适用于半导体存储器件的数据输出缓冲器包括耦合到第一数据信号和第一控制信号（例如，输出使能信号）的第一输入电路和耦合到第二数据信号的第二输入电路，第二数据信号是 第一数据信号和第一控制信号的反相。 数据输出缓冲器还包括响应于第一输入电路的输出的上拉电路，用于选择性地将数据输出节点升高到高电压电平，例如Vcc，以及响应于第二输出的输出的下拉电路 输入电路，用于选择性地将数据输出节点降低到低电压电平，例如Vss。 数据输出缓冲器还包括预置电路，其包括响应于第一输入电路的输出的第一预设控制电路和第二控制信号，例如反相输出使能信号，用于选择性地将数据输出节点从低电压 电平到中间电压电平，例如1/2Vcc，以及响应于第二输入电路的输出和第二控制信号的第二预设控制电路，用于选择性地将数据输出节点从高电压电平降低到中间电压 水平。 预置控制电路有利地用于在输出使能信号的有效状态期间将数据输出节点维持在中间电压电平，而不产生任何DC电流，从而消除当前可用的数据输出缓冲器的噪声和可靠性问题。

    Electrically programmable internal power voltage generating circuit
    4.
    发明授权
    Electrically programmable internal power voltage generating circuit 失效
    电可编程内部电源电压发生电路

    公开(公告)号：US5396113A

    公开(公告)日：1995-03-07

    申请号：US922549

    申请日：1992-07-31

    Applicant: Yong-Bo Park ,  Byeong-Yun Kim ,  Hyung-Kyu Lim

    Inventor： Yong-Bo Park ,  Byeong-Yun Kim ,  Hyung-Kyu Lim

    IPC: G11C11/413 ,  G05F1/56 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H03K3/01 ,  G11C7/00

    CPC classification number: G11C5/147

    Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.

    Abstract translation: 半导体存储器件的内部电源电压产生电路可以由提供内部电源电压int的电压感测电路（100）和参考电压控制器（300）构成。 给定参考电压幅值Vref的VCC和外部电源电压振幅分频。 VCC。 因此，当将芯片的工作电压上的高电压施加到芯片的焊盘（10）时，内部电源电压升高到外部电源电压的电平。 因此，当在“老化试验”期间将应力加到芯片上时，容易检测到有缺陷的芯片。 因此，可以提高经过后期制造测试的那些半导体存储器件的可靠性。

    Data output buffer circuit for byte-wide memory
    5.
    发明授权
    Data output buffer circuit for byte-wide memory 失效
    用于字节宽度存储器的数据输出缓冲电路

    公开(公告)号：US4972100A

    公开(公告)日：1990-11-20

    申请号：US332005

    申请日：1989-03-31

    Applicant: Hyung-Kyu Lim ,  Hyong-Gon Lee ,  Keon-Soo Kim

    Inventor： Hyung-Kyu Lim ,  Hyong-Gon Lee ,  Keon-Soo Kim

    IPC: G11C11/417 ,  G11C7/10 ,  G11C11/40 ,  G11C11/409 ,  H03F3/04 ,  H03K17/16 ,  H03K17/687

    CPC classification number: H03K17/6872 ,  G11C7/1051 ,  H03K17/163

    Abstract: An output buffer circuit for a byte wide memory is disclosed, including a circuit for delaying the falling or rising time of the gate voltage of a pull-up transistor of an output driver, located between a p-channel transistor and an n-channel transistor of the pull-up inverter; and a circuit for delaying the rising time of the gate voltage of a pull-down transistor of the output driver, located between a p-channel transistor and an n-channel transistor of the pull-down inverter. The disclosed delay circuits may include a depletion transistor having a gate and a source connected to each other. Through the provision of such delay mechanisms, the noise generations in both the power lines and the ground lines are reduced.

    Abstract translation: 公开了一种用于字节宽的存储器的输出缓冲电路，包括用于延迟位于p沟道晶体管和n沟道晶体管之间的输出驱动器的上拉晶体管的栅极电压的下降或上升时间的电路 的上拉变频器; 以及用于延迟位于下拉反相器的p沟道晶体管和n沟道晶体管之间的输出驱动器的下拉晶体管的栅极电压的上升时间的电路。 公开的延迟电路可以包括具有彼此连接的栅极和源极的耗尽晶体管。 通过提供这种延迟机制，电力线和地线中的噪声产生减少。

    Circuit for designating an operating mode of a semiconductor memory device
    7.
    发明授权
    Circuit for designating an operating mode of a semiconductor memory device 失效

    公开(公告)号：US5901094A

    公开(公告)日：1999-05-04

    申请号：US631854

    申请日：1996-04-10

    Applicant: Choong-Sun Chin ,  Hyung-Kyu Lim

    Inventor： Choong-Sun Chin ,  Hyung-Kyu Lim

    IPC: G11C11/407 ,  G11C7/10 ,  G11C17/18 ,  G11C7/00

    CPC classification number: G11C17/18 ,  G11C7/1045

    Abstract: A circuit for designating an operating mode of a packaged semiconductor memory device includes a first fuse mounted on the device. A plurality of pads mounted on the device are accessible to a user after the device is packaged. A mode selection circuit generates a first signal when the first fuse is open and a second signal when the first fuse is closed. A first-fuse opening circuit is operably connected to the pads and opens the first fuse responsive to a predetermined first-fuse cutting signal on the pads. In another aspect of the invention, a second fuse may be opened responsive to a predetermined second-fuse cutting signal on the pads. When the second fuse opens, the first-fuse opening circuit is disabled to prevent accidental opening of the first fuse when the desired operating mode requires the first fuse to be maintained intact.

    Redundancy circuit for use in a semiconductor memory device
    8.
    发明授权
    Redundancy circuit for use in a semiconductor memory device 失效
    用于半导体存储器件的冗余电路

    公开(公告)号：US4794568A

    公开(公告)日：1988-12-27

    申请号：US44702

    申请日：1987-05-01

    Applicant: Hyung-Kyu Lim ,  Jae-Yeong Do ,  Rustam Mehta

    Inventor： Hyung-Kyu Lim ,  Jae-Yeong Do ,  Rustam Mehta

    IPC: H01L27/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L27/00 ,  G11C7/00

    CPC classification number: G11C29/785

    Abstract: A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

    Abstract translation: 正常解码器和具有地址程序设备的冗余解码器用于替换坏小区。 地址编程设备的数量比用于选择正常行或列的输入地址位数多一个。 附加程序设备的输入信号与其他程序设备之一的输入信号互补。 程序设备的程序有两个步骤来修复故障单元。 为了提高冗余的可靠性，在程序设备中使用的非易失性存储元件是连接四个单元FLOTOX型非易失性存储器件的桥。

    Circuit for designating an operating mode of a semiconductor memory device
    9.
    发明授权
    Circuit for designating an operating mode of a semiconductor memory device 有权
    用于指定半导体存储器件的工作模式的电路

    公开(公告)号：US6141282A

    公开(公告)日：2000-10-31

    申请号：US234779

    申请日：1999-01-20

    Applicant: Choong-Sun Chin ,  Hyung-Kyu Lim

    Inventor： Choong-Sun Chin ,  Hyung-Kyu Lim

    IPC: G11C11/407 ,  G11C7/10 ,  G11C17/18 ,  G11C7/00

    CPC classification number: G11C17/18 ,  G11C7/1045

    Abstract: A circuit for designating an operating mode of a packaged semiconductor memory device includes a first fuse mounted on the device. A plurality of pads mounted on the device are accessible to a user after the device is packaged. A mode selection circuit generates a first signal when the first fuse is open and a second signal when the first fuse is closed. A first-fuse opening circuit is operably connected to the pads and opens the first fuse responsive to a predetermined first-fuse cutting signal on the pads. In another aspect of the invention, a second fuse may be opened responsive to a predetermined second-fuse cutting signal on the pads. When the second fuse opens, the first-fuse opening circuit is disabled to prevent accidental opening of the first fuse when the desired operating mode requires the first fuse to be maintained intact.

    Abstract translation: 用于指定封装半导体存储器件的操作模式的电路包括安装在该器件上的第一熔丝。 安装在设备上的多个焊盘在设备被封装之后可被用户访问。 模式选择电路当第一保险丝断开时产生第一信号，并且当第一保险丝闭合时产生第二信号。 第一保险丝开路电路可操作地连接到焊盘，并响应于焊盘上的预定的第一熔丝切割信号而打开第一熔丝。 在本发明的另一方面，可以响应于焊盘上的预定的第二熔丝切割信号来打开第二熔丝。 当第二个保险丝打开时，当所需的操作模式要求第一个保险丝保持完好时，第一个保险丝断开电路被禁用以防止意外打开第一个保险丝。

    Auto-program circuit in a nonvolatile semiconductor memory device
    10.
    发明授权
    Auto-program circuit in a nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件中的自动编程电路

    公开(公告)号：US5642309A

    公开(公告)日：1997-06-24

    申请号：US526422

    申请日：1995-09-11

    Applicant: Jin-Ki Kim ,  Hyung-Kyu Lim ,  Sung-Soo Lee

    Inventor： Jin-Ki Kim ,  Hyung-Kyu Lim ,  Sung-Soo Lee

    IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C29/00 ,  G11C29/12 ,  G11C7/00 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/30

    Abstract: An auto-program voltage generator in a nonvolatile semiconductor memory having a plurality of floating gate type memory cells, program circuit for programming selected memory cells, and program verification circuit for verifying whether or not the selected memory cells are successfully programmed comprises a high voltage generator for generating a program voltage, a trimming circuit for detecting the level of the program voltage to increase sequentially the program voltage within a predetermined voltage range every time the selected memory cells are not successfully programmed, a comparing circuit for comparing the detected voltage level with a reference voltage and then generating a comparing signal, and a high voltage generation control circuit for activating the high voltage generator in response to the comparing signal.

    Abstract translation: 一种具有多个浮动型存储单元的非易失性半导体存储器中的自动编程电压发生器，用于编程所选存储单元的程序电路和用于验证所选存储单元是否被成功编程的程序验证电路包括高电压发生器 用于产生编程电压的微调电路，用于检测编程电压的电平以在每次所选存储单元未成功编程时在预定电压范围内依次增加编程电压的微调电路;用于将检测的电压电平与 参考电压，然后产生比较信号;以及高电压发生控制电路，用于响应于比较信号激活高电压发生器。

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