Abstract:
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.
Abstract:
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.
Abstract:
A computer-implemented method for generating code based on a graphical model may include: translating the graphical model into a graphical model code, the graphical model code including a first graphical model code function; performing a lookup of the first graphical model code function in a hardware specific library, the hardware specific library comprising a plurality of relationships between graphical model code functions and hardware specific functions, where the first graphical model code function is one of the graphical model code functions; obtaining a matched hardware specific function based on the lookup, wherein the matched hardware specific function is one of the hardware specific functions from the hardware specific library; and modifying the graphical model code based on the matched hardware specific function.
Abstract:
Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.
Abstract:
A method and apparatus to generate code to represent a graphical model formed of multiple graphical modeling components and at least one variable-sized signal is presented. Each variable-sized signal is represented using a size-vector in the generated code. The generated code is optimized by representing multiple variable-sized signals with the same size-vector such that at least two variable-sized signals share a size-vector in the generated code. The size of the variable-sized signal is capable of changing during the execution of the graphical model. The method and apparatus also identifies the owners of the variable-sized signals.
Abstract:
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.
Abstract:
A computer-implemented method for generating code based on a graphical model may include: translating the graphical model into a graphical model code, the graphical model code including a first graphical model code function; performing a lookup of the first graphical model code function in a hardware specific library, the hardware specific library comprising a plurality of relationships between graphical model code functions and hardware specific functions, where the first graphical model code function is one of the graphical model code functions; obtaining a matched hardware specific function based on the lookup, wherein the matched hardware specific function is one of the hardware specific functions from the hardware specific library; and modifying the graphical model code based on the matched hardware specific function.
Abstract:
Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.