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    Compliant surface layer for flip-chip electronic packages and method for forming same
    4.
    发明授权
    Compliant surface layer for flip-chip electronic packages and method for forming same 失效
    适用于倒装芯片电子封装的表面层及其形成方法

    公开(公告)号：US06191952B1

    公开(公告)日：2001-02-20

    申请号：US09067708

    申请日：1998-04-28

    申请人： Miquel A. Jimarez ,  Eric A. Johnson ,  Li Li ,  Jan Obrzut

    发明人： Miquel A. Jimarez ,  Eric A. Johnson ,  Li Li ,  Jan Obrzut

    IPC分类号： H05K118

    CPC分类号： H01L23/49894 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

    摘要： Flip-chip electronic packages are provided with a compliant surface layer, normally positioned between an underfill layer and a substrate such as a chip carrier or a printed circuit board or card, which reduces stress and strain resulting from differences in coefficients of thermal expansion between the chip and substrate. The compliant layer, which should have a storage modulus of less than ½ the modulus of the substrate, preferably between about 50,000 psi and about 20,000 psi, may comprise rubbery materials such as silicone, virco-plastic polymers such as polytetrafluoroethylene or interpenetrating polymer networks (IPNs). Photosensitive IPNs used for solder marks are preferred.

    摘要翻译： 倒装芯片电子封装设置有通常位于底部填充层和诸如芯片载体或印刷电路板或卡之类的基板之间的顺应性表面层，其减少了由于两者之间的热膨胀系数差异导致的应力和应变 芯片和基板。 应该具有小于衬底模量的1/2的柔性层，优选在约50,000psi和约20,000psi之间的弹性层可以包括橡胶状材料，例如硅树脂，诸如聚四氟乙烯的环氧塑料聚合物或互穿聚合物网络（ IPN）。 用于焊锡标记的光敏IPN是优选的。

    Method for determining interconnection resistance of wire leads in electronic packages
    6.
    发明授权
    Method for determining interconnection resistance of wire leads in electronic packages 失效
    确定电子封装中导线的互连电阻的方法

    公开(公告)号：US5786700A

    公开(公告)日：1998-07-28

    申请号：US650505

    申请日：1996-05-20

    申请人： Keh-Chee Jen ,  Jan Obrzut

    发明人： Keh-Chee Jen ,  Jan Obrzut

    IPC分类号： G01R31/28 ,  G01R27/08 ,  G01R31/26

    CPC分类号： G01R31/2853

    摘要： A process determines a linear interconnection resistance R between two external access points of an electronic device. The device comprises a chip, a chip carrier and wiring between the chip and carrier. The chip comprises an ESD device such as a diode which is electrically connected between the two access points. To begin the process, various currents are injected from one of the access points to another and corresponding voltages are measured across the two access points. Alternately, various voltages are applied from one access point to the other and corresponding currents are measured. The applied voltages and injected currents all forward bias the ESD device. These current-voltage relationships are applied to an interconnection model algorithm to yield the interconnection resistance. The interconnection model algorithm is derived from an interconnection model equation using least squares as a maximum likelihood estimator applied to the interconnection model equation to deliver absolute roots of the interconnection model algorithm. The interconnection model equation models the circuit comprising the interconnection resistance and the ESD device except that the nonlinear parameters of the ESD device is untangled from the linear interconnection resistance.

    摘要翻译： 一个过程确定电子设备的两个外部接入点之间的线性互连电阻R。 该器件包括芯片，芯片载体和芯片与载体之间的布线。 该芯片包括电连接在两个接入点之间的诸如二极管之类的ESD器件。 为了开始该过程，将各种电流从接入点之一注入到另一个，并在两个接入点上测量相应的电压。 或者，从一个接入点向另一个接入点施加各种电压，并测量相应的电流。 所施加的电压和注入电流都正向偏置ESD器件。 这些电流 - 电压关系被应用于互连模型算法以产生互连电阻。 互连模型算法从互连模型方程得出，使用最小二乘作为应用于互连模型方程的最大似然估计器来传递互连模型算法的绝对根。 互连模型方程式对包括互连电阻和ESD器件的电路进行建模，除了ESD器件的非线性参数从线性互连电阻解开。