公开(公告)号：US4820936A

公开(公告)日：1989-04-11

申请号：US94363

申请日：1987-09-08

申请人： Hendrikus J. M. Veendrick ,  Cornelis G. L. M. Van Der Sanden ,  Arie Slob

发明人： Hendrikus J. M. Veendrick ,  Cornelis G. L. M. Van Der Sanden ,  Arie Slob

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/407 ,  H01L21/822 ,  H01L27/08 ,  H02M3/07 ,  H03K3/03 ,  H03K17/16 ,  H01L27/02 ,  H03K17/06 ,  H03K17/14

CPC分类号： H03K3/0315 ,  G05F3/205

摘要： In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.

公开(公告)号：US4536948A

公开(公告)日：1985-08-27

申请号：US602793

申请日：1984-04-23

申请人： Ties S. Te Velde ,  Arie Slob

发明人： Ties S. Te Velde ,  Arie Slob

IPC分类号： G11C17/06 ,  G11C17/12 ,  G11C17/14 ,  H01H85/046 ,  H01L21/308 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L27/12 ,  H01L21/90

CPC分类号： H01H85/046 ,  G11C17/12 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A blowable fuse is provided over a part of its length separately from the walls of an enveloping cavity and separated from a supporting member. As a result of this the fuse is readily thermally isolated so that it fuses more rapidly and with less energy. In addition, a semiconductor circuit element, for example a Schottky diode, can be realized below a bridging part of a conductor which serves as an upper wall of the cavity, which results in a high bit density.

摘要翻译： 一个可熔断的保险丝被设置在其长度的一部分上，与包络腔的壁分开并与支撑构件分离。 因此，保险丝易于热隔离，因此它可以更快速地熔化和更少的能量。 此外，半导体电路元件例如肖特基二极管可以在用作空腔的上壁的导体的桥接部分下面实现，这导致高的比特密度。

公开(公告)号：US4283837A

公开(公告)日：1981-08-18

申请号：US29424

申请日：1979-04-12

申请人： Arie Slob

发明人： Arie Slob

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/08 ,  H01L21/365 ,  H01L21/42 ,  H01L21/44

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L23/53271 ,  H01L24/05 ,  H01L29/0804 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/14

摘要： A semiconductor device includes a silicon substrate having an insulating layer with a window. A silicon layer is deposited on the insulating layer and on the silicon substrate surface in the window. This silicon layer has n-type and p-type conductive layer parts which adjoin each other within the window and which each serve as both a connection conductor and an electrode of an active zone of the device. Semiconductor devices in accordance with the invention feature very small surface areas, and are thus particularly suitable for high frequency operation.

摘要翻译： 半导体器件包括具有带窗口的绝缘层的硅衬底。 硅层沉积在窗口中的绝缘层和硅衬底表面上。 该硅层具有在窗内彼此相邻的n型和p型导电层部分，并且各自用作连接导体和器件活性区的电极。 根据本发明的半导体器件具有非常小的表面积，因此特别适用于高频操作。

公开(公告)号：US3930909A

公开(公告)日：1976-01-06

申请号：US527236

申请日：1974-11-26

申请人： Albert Schmitz ,  Cornelis Mulder ,  Arie Slob

发明人： Albert Schmitz ,  Cornelis Mulder ,  Arie Slob

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/82 ,  H01L21/8228 ,  H01L27/082 ,  H01L21/20 ,  H01L21/22 ,  H01L27/04

CPC分类号： H01L21/761 ,  H01L21/74 ,  H01L21/82 ,  H01L21/82285 ,  H01L27/0826

摘要： A method of making a semiconductor device is described in which opposite-type impurities are introduced into the same surface of a substrate in such manner that the region of impurities of the opposite-type to that of the substrate overlaps completely the other substrate surface region. Then an epitaxial layer is grown on the surface of the substrate. There is thus formed two buried layers of which the one with the same type conductivity of the substrate is completely separated and isolated from the latter by the buried layer of opposite-type conductivity. Methods are also described for the manufacture of complementary bipolar transistors, in which the pnp type is made by the above described method.

公开(公告)号：US4161745A

公开(公告)日：1979-07-17

申请号：US837032

申请日：1977-09-27

申请人： Arie Slob

发明人： Arie Slob

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/08 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

CPC分类号： H01L21/28525 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L23/53271 ,  H01L24/05 ,  H01L29/0804 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/14

摘要： A semiconductor device includes a silicon substrate having an insulating layer with a window. A silicon layer is deposited on the insulating layer and on the silicon substrate surface in the window. This silicon layer has n-type and p-type conductive layer parts which adjoin each other within the window and which each serve as both a connection conductor and an electrode of an active zone of the device. Semiconductor devices in accordance with the invention feature very small surface areas, and are thus particularly suitable for high frequency operation.

摘要翻译： 半导体器件包括具有带窗口的绝缘层的硅衬底。 硅层沉积在窗口中的绝缘层和硅衬底表面上。 该硅层具有在窗内彼此相邻的n型和p型导电层部分，并且各自用作连接导体和器件活性区的电极。 根据本发明的半导体器件具有非常小的表面积，因此特别适用于高频操作。

公开(公告)号：US4122542A

公开(公告)日：1978-10-24

申请号：US776252

申请日：1977-03-10

申请人： Ferdinand Camerik ,  Cornelis Maria Hart ,  Arie Slob

发明人： Ferdinand Camerik ,  Cornelis Maria Hart ,  Arie Slob

IPC分类号： G11C11/40 ,  G11C11/411 ,  G11C11/414 ,  H01L27/00 ,  H01L27/02 ,  H01L27/102 ,  H03F3/04 ,  H03K3/012 ,  H03K3/289 ,  H03K19/091

CPC分类号： H03K19/091 ,  G11C11/40 ,  G11C11/4113 ,  G11C11/414 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/1022 ,  H01L27/1025 ,  H03F3/04 ,  H03K3/012 ,  H03K3/289

摘要： An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and a row selection line connected to the emitter regions of the load transistors in an associated row of memory cells.

摘要翻译： 一种具有多个存储单元的集成电路存储器阵列，该多个存储单元包括一个导电类型的两个交叉耦合晶体管，另一个导电类型的负载晶体管，以及位线，其通过一个连接到一个交叉耦合晶体管的基极区域 位线晶体管。 该阵列具有公共节点，用于为每个存储器单元直接互连负载晶体管的所有基极区域和交叉耦合晶体管的发射极区域; 以及连接到相关行的存储器单元中的负载晶体管的发射极区的行选择线。

公开(公告)号：US4878202A

公开(公告)日：1989-10-31

申请号：US187612

申请日：1988-04-28

申请人： Arie Slob

发明人： Arie Slob

IPC分类号： H01L27/10 ,  G11C19/28 ,  G11C19/38 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/762 ,  H04N5/335

CPC分类号： G11C19/287 ,  G11C19/38 ,  G11C27/04

摘要： A charge-coupled memory of the SPS type, in which the input of the series input register is coupled so as to be switchable to an n-bit shift register. The data can thus be read in directly or with a certain delay via the shift register. If an uninterrupted flow of bits is supplied, for example video information, a pause, during which no bits appear at the input of the input register, can be obtained by switching on the shift register in the supply of information to the input register, without information being lost. This pause can be utilized to transport information already read in to the parallel section. As a result, a matrix organization can be given to the memory, in which event the dissipation is lower, the transfer losses are smaller and at the same time a gain in surface area is obtained.

公开(公告)号：US4528583A

公开(公告)日：1985-07-09

申请号：US601894

申请日：1984-04-19

申请人： Ties S. te Velde ,  Arie Slob

发明人： Ties S. te Velde ,  Arie Slob

IPC分类号： G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01H1/00 ,  H01H59/00 ,  H01L21/308 ,  H01L21/822 ,  H01L23/525 ,  H01L23/58 ,  H01L27/04 ,  H01L27/10 ,  H01L27/12 ,  G11C11/40 ,  H01L23/52

CPC分类号： H01L23/585 ,  G11C17/16 ,  H01H59/0009 ,  H01L23/5256 ,  H01H1/0036 ,  H01L2924/0002

摘要： A programmable semiconductor device having a microswitch (11) which over a part of its length is provided separately from a bridging conductor (10), for example, a word line and a supporting element. Since the dimensions of the switch (11) and the conductor (10) are independent of each other, the resistance of the conductor (10) may be low so that programmable memories having a high read-in and read-out rate are obtained. In addition the circuit element, for example a Schottky diode (3, 8) can be realized below the bridging part (12) of the conductor (10), which results in a high bit density. Since the switch (11) is present below the conductor (10) the assembly can be passivated in the unprogrammed state by means of a protective layer (20), so that the switch 11 is encapsulated in a hollow space (21).

摘要翻译： 具有在其长度的一部分上的微动开关（11）的可编程半导体器件与例如字线和支撑元件的桥接导体（10）分开设置。 由于开关（11）和导体（10）的尺寸彼此独立，导体（10）的电阻可能较低，从而获得具有高读入和读出速率的可编程存储器。 此外，可以在导体（10）的桥接部分（12）下面实现电路元件，例如肖特基二极管（3,8），这导致高比特密度。 由于开关（11）存在于导体（10）的下面，组件可以通过保护层（20）以未编程的状态被钝化，使得开关11被封装在中空空间（21）中。

公开(公告)号：US4460914A

公开(公告)日：1984-07-17

申请号：US258112

申请日：1981-04-27

申请人： Ties S. te Velde ,  Arie Slob

发明人： Ties S. te Velde ,  Arie Slob

IPC分类号： G11C17/06 ,  G11C17/12 ,  G11C17/14 ,  H01H85/046 ,  H01L21/308 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L27/12 ,  G11C11/40

CPC分类号： H01H85/046 ,  G11C17/12 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A blowable fuse is provided over a part of its length separately from the walls of an enveloping cavity and separated from a supporting member. As a result of this the fuse is readily thermally isolated so that it fuses more rapidly and with less energy. In addition, a semiconductor circuit element, for example a Schottky diode, can be realized below a bridging part of a conductor which serves as an upper wall of the cavity, which results in a high bit density.

摘要翻译： 一个可熔断的保险丝被设置在其长度的一部分上，与包络腔的壁分开并与支撑构件分离。 因此，保险丝易于热隔离，因此它可以更快速地熔化和更少的能量。 此外，半导体电路元件例如肖特基二极管可以在用作空腔的上壁的导体的桥接部分下面实现，这导致高的比特密度。

公开(公告)号：US4286177A

公开(公告)日：1981-08-25

申请号：US876219

申请日：1978-02-09

申请人： Cornelis M. Hart ,  Arie Slob

发明人： Cornelis M. Hart ,  Arie Slob

IPC分类号： H03F3/185 ,  G11C11/34 ,  G11C11/411 ,  G11C11/413 ,  G11C11/414 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L27/102 ,  H01L29/47 ,  H01L29/72 ,  H01L29/73 ,  H01L29/872 ,  H03F3/04 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03K3/012 ,  H03K3/288 ,  H03K3/289 ,  H03K19/08 ,  H03K19/091 ,  H04R25/00

CPC分类号： H03K19/091 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/413 ,  G11C11/414 ,  H01L27/00 ,  H01L27/0233 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0821 ,  H01L27/1025 ,  H01L29/72 ,  H03F3/04 ,  H03K19/08 ,  H03K3/012 ,  H03K3/288 ,  H03K3/289 ,  H04R25/00 ,  Y10S148/087

摘要： An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

摘要翻译： 集成注入逻辑集成电路，其中通过电流注入器提供偏置电流。 电流注入器是多层结构，其中通过经由整流结点的电荷载体的注入和收集来提供电流到被偏置的电路的预定区域。 这样的区域优选地被电荷载体偏置，电荷载体由电流注入器的一个层从这些区域收集。 电路还优选地包括用于减小从预定区域的载流子注入的区域。