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    MEMORY MODULE, MEMORY MODULE SOCKET AND MAINBOARD USING SAME
    1.
    发明申请
    MEMORY MODULE, MEMORY MODULE SOCKET AND MAINBOARD USING SAME 审中-公开
    存储模块，存储模块插座和使用相同的主板

    公开(公告)号：US20090209134A1

    公开(公告)日：2009-08-20

    申请号：US12428530

    申请日：2009-04-23

    Applicant: Sung-Joo PARK ,  Kyoung-Sun KIM ,  Jung-Joon LEE ,  Jea-Eun LEE

    Inventor： Sung-Joo PARK ,  Kyoung-Sun KIM ,  Jung-Joon LEE ,  Jea-Eun LEE

    IPC: H01R13/66

    CPC classification number: H01R12/83 ,  H01R13/62988 ,  H01R13/631 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09954 ,  H05K2201/10159

    Abstract: A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.

    Abstract translation: 存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一 连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器 模块插座平行于主板的主表面。

    Memory module, memory module socket and mainboard using same
    2.
    发明授权
    Memory module, memory module socket and mainboard using same 有权
    内存模块，内存模块插座和主板使用相同

    公开(公告)号：US07540743B2

    公开(公告)日：2009-06-02

    申请号：US11836286

    申请日：2007-08-09

    Applicant: Sung-Joo Park ,  Kyoung-Sun Kim ,  Jung-Joon Lee ,  Jea-Eun Lee

    Inventor： Sung-Joo Park ,  Kyoung-Sun Kim ,  Jung-Joon Lee ,  Jea-Eun Lee

    IPC: H01R12/00

    CPC classification number: H01R12/83 ,  H01R13/62988 ,  H01R13/631 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09954 ,  H05K2201/10159

    Abstract: A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.

    Abstract translation: 存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一 连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器 模块插座平行于主板的主表面。

    Memory module having improved arrangement of discrete devices
    3.
    发明申请
    Memory module having improved arrangement of discrete devices 审中-公开
    具有改进的离散器件布置的存储器模块

    公开(公告)号：US20080030943A1

    公开(公告)日：2008-02-07

    申请号：US11708591

    申请日：2007-02-21

    Applicant: Kyoung-sun Kim ,  Sung-joo Park ,  Jung-joon Lee ,  Jea-eun Lee

    Inventor： Kyoung-sun Kim ,  Sung-joo Park ,  Jung-joon Lee ,  Jea-eun Lee

    IPC: H05K1/14

    CPC classification number: H05K1/181 ,  G11C5/04 ,  H01L2224/16225 ,  H05K1/023 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

    Abstract: Embodiments of the invention provide memory module having an improved arrangement of discrete devices. In one embodiment, the invention provides a memory module comprising a board; a plurality of tabs disposed adjacent to a first edge of the board and disposed on a first surface of the board; and a memory pad region disposed on the first surface and comprising memory chip pads, wherein each memory chip pad is electrically connected to at least one of the tabs. The memory module further comprises discrete devices corresponding to the memory pad region, wherein the discrete devices corresponding to the memory pad region are disposed on only one side of the memory pad region. In the memory module, each of the discrete devices is electrically connected to at least one of the tabs and at least one of the memory chip pads.

    Abstract translation: 本发明的实施例提供了具有改进的离散设备布置的存储器模块。 在一个实施例中，本发明提供一种包括板的存储器模块; 多个突出部，其布置成邻近所述板的第一边缘并且设置在所述板的第一表面上; 以及存储器焊盘区域，其设置在所述第一表面上并且包括存储器芯片焊盘，其中每个存储器芯片焊盘电连接到所述突片中的至少一个。 存储器模块还包括对应于存储器焊盘区域的离散器件，其中对应于存储器焊盘区域的分立器件仅设置在存储器焊盘区域的一侧。 在存储器模块中，每个分立器件电连接到至少一个接头片和至少一个存储器芯片焊盘。

    MEMORY MODULE, MEMORY MODULE SOCKET AND MAINBOARD USING SAME
    5.
    发明申请
    MEMORY MODULE, MEMORY MODULE SOCKET AND MAINBOARD USING SAME 有权
    存储模块，存储模块插座和使用相同的主板

    公开(公告)号：US20080038961A1

    公开(公告)日：2008-02-14

    申请号：US11836286

    申请日：2007-08-09

    Applicant: Sung-Joo PARK ,  Kyoung-Sun KIM ,  Jung-Joon LEE ,  Jea-Eun LEE

    Inventor： Sung-Joo PARK ,  Kyoung-Sun KIM ,  Jung-Joon LEE ,  Jea-Eun LEE

    IPC: H01R24/00

    CPC classification number: H01R12/83 ,  H01R13/62988 ,  H01R13/631 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09954 ,  H05K2201/10159

    Abstract: A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.

    Abstract translation: 存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一 连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器 模块插座平行于主板的主表面。

    Memory module
    6.
    发明申请
    Memory module 有权
    内存模块

    公开(公告)号：US20090154212A1

    公开(公告)日：2009-06-18

    申请号：US12292700

    申请日：2008-11-24

    Applicant: Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    Inventor： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00

    CPC classification number: G11C7/20 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/105

    Abstract: A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.

    Abstract translation: 存储器模块包括存储器模块板和存储器模块板上的多个存储器件。 存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。 每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及 多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME
    7.
    发明申请
    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US20120014156A1

    公开(公告)日：2012-01-19

    申请号：US13110161

    申请日：2011-05-18

    Applicant: Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    Inventor： Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC: G11C5/02 ,  G11C7/10 ,  H03L5/00

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    Abstract translation: 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    Data receiver, semiconductor device and memory device including the same
    8.
    发明授权
    Data receiver, semiconductor device and memory device including the same 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US08559241B2

    公开(公告)日：2013-10-15

    申请号：US13110161

    申请日：2011-05-18

    Applicant: Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    Inventor： Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC: G11C7/10

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    Abstract translation: 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    Memory module
    9.
    发明授权
    Memory module 有权
    内存模块

    公开(公告)号：US07859879B2

    公开(公告)日：2010-12-28

    申请号：US12292700

    申请日：2008-11-24

    Applicant: Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    Inventor： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    IPC: G11C5/00

    CPC classification number: G11C7/20 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/105

    Abstract: A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.

    Abstract translation: 存储器模块包括存储器模块板和存储器模块板上的多个存储器件。 存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。 每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及 多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

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