公开(公告)号：US07968941B2

公开(公告)日：2011-06-28

申请号：US12412659

申请日：2009-03-27

申请人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

发明人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681

摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.

摘要翻译： 半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。

公开(公告)号：US20090242981A1

公开(公告)日：2009-10-01

申请号：US12412659

申请日：2009-03-27

申请人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

发明人： Kazunori Fujita ,  Tomio Yamashita ,  Haruki Yoneda ,  Kazuhiro Sasada

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681

摘要： A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.

摘要翻译： 半导体器件包括：外延层; 形成在外延层中的体层，其包括沟道区; 源层，叠加在体层上; 形成在外延层上的栅极绝缘体，其围绕源极层呈环形; 通过栅极绝缘体形成的栅电极; 在外延层中形成的漂移层，该外延层围绕主体层呈环状; 以及形成在所述外延层的表面中并且与所述源极层相对设置的漏极层。 主体层被布置成使得栅极宽度方向上的端部处的边界表面与栅极绝缘体的下表面接触。 栅极绝缘体至少在栅极绝缘体与栅极宽度端部处的主体层的边界面接触的部分中具有比栅极长度方向上的沟道区域上方的部分更厚的厚膜部分 方向。

公开(公告)号：US20050200711A1

公开(公告)日：2005-09-15

申请号：US11074863

申请日：2005-03-09

申请人： Ryu Shimizu ,  Kazuhiro Sasada ,  Masahiro Oda

发明人： Ryu Shimizu ,  Kazuhiro Sasada ,  Masahiro Oda

IPC分类号： H01L27/148 ,  H04N5/225

CPC分类号： H01L27/14614 ,  H01L27/14806 ,  H01L27/1485 ,  H04N5/335 ,  H04N5/372

摘要： A solid state imaging device includes photoelectric conversion portions for performing photoelectric conversion, and transfer portions for transferring signal charge occurring at the photoelectric conversion portions. Each transfer portion includes a transfer electrode formed of polysilicon film or the like, and an insulating coating film formed of a material such as a silicon nitride film and so forth, which has a higher relative dielectric constant than that of the silicon oxide, for coating the bottom face, the upper face, and both side faces, of the transfer electrode. The silicon nitride film is formed with a film thickness which is greater than 0 nm and smaller than 60 nm, on both sides of the transfer electrode.

摘要翻译： 固态成像装置包括用于进行光电转换的光电转换部分和用于传送在光电转换部分发生的信号电荷的转印部分。 每个转印部分包括由多晶硅膜等形成的转印电极和由诸如氮化硅膜等的材料形成的绝缘涂膜，其具有比氧化硅更高的相对介电常数，用于涂覆 转印电极的底面，上表面和两个侧面。 在转移电极的两侧，形成厚度大于0nm且小于60nm的氮化硅膜。

公开(公告)号：US06890831B2

公开(公告)日：2005-05-10

申请号：US10449726

申请日：2003-06-02

申请人： Mayumi Nakasato ,  Makoto Izumi ,  Kazuhiro Sasada ,  Masahiro Oda ,  Toru Dan

发明人： Mayumi Nakasato ,  Makoto Izumi ,  Kazuhiro Sasada ,  Masahiro Oda ,  Toru Dan

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/76235 ,  H01L21/823878

摘要： A method of fabricating a semiconductor device capable of improving reliability of a gate insulator film is obtained. This method of fabricating a semiconductor device comprises a step of forming a gate insulator film on the main surface of a semiconductor layer by heat treatment, and the step of forming the gate insulator film includes a step of performing the heat treatment in an atmosphere containing oxidizing gas at a temperature exceeding the temperature causing viscous flow of the gate insulator film thereby forming the gate insulator film on the main surface of the semiconductor layer.

摘要翻译： 获得了能够提高栅极绝缘膜的可靠性的半导体装置的制造方法。 这种制造半导体器件的方法包括通过热处理在半导体层的主表面上形成栅极绝缘膜的步骤，并且形成栅绝缘膜的步骤包括在包含氧化物的气氛中进行热处理的步骤 气体温度超过导致栅极绝缘膜的粘性流动的温度，从而在半导体层的主表面上形成栅极绝缘膜。

公开(公告)号：US06995434B2

公开(公告)日：2006-02-07

申请号：US10671458

申请日：2003-09-29

申请人： Ryosuke Usui ,  Kazuhiro Sasada

发明人： Ryosuke Usui ,  Kazuhiro Sasada

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/28114 ,  H01L21/28052 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665

摘要： A semiconductor device capable of suppressing increase of the capacitance while suppressing a thin-line effect of a silicide film is obtained. This semiconductor device comprises a first silicon layer formed on a semiconductor substrate through a gate insulator film with an upper portion and a lower portion larger in width than a central portion for serving as a gate electrode and a first silicide film formed on the first silicon layer for serving as the gate electrode.

摘要翻译： 获得能够抑制硅化物薄膜的细线效应的同时抑制电容增加的半导体装置。 该半导体器件包括通过栅极绝缘膜形成在半导体衬底上的第一硅层，其上部和宽度大于用作栅电极的中心部分的下部，以及形成在第一硅层上的第一硅化物膜 用作栅电极。

公开(公告)号：US06613635B2

公开(公告)日：2003-09-02

申请号：US10015756

申请日：2001-12-17

申请人： Masahiro Oda ,  Kazuhiro Sasada

发明人： Masahiro Oda ,  Kazuhiro Sasada

IPC分类号： H01L21336

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

摘要： Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating the semiconductor substrate. Embodiments include increasing the threshold voltage in the upper corner portion of the trench in an n-channel transistor, previously increased by rounding oxidation, and introducing a p-type impurity, thereby canceling the threshold voltage reduction resulting from diffusion of the impurity during heat-treating the semiconductor substrate. In a p-channel transistor, the threshold voltage in the upper corner portion of the trench is increased by rounding oxidation thereby canceling the threshold voltage reduction resulting from introduction of the p-type first impurity into both upper corner portions of the trench.

摘要翻译： 沟槽隔离的上角部的阈值电压波动通过热氧化对沟槽的上角部进行四舍五入，将第一杂质引入槽的两个上角部并对半导体衬底进行热处理来抑制。 实施例包括增加先前通过四舍五入氧化增加的n沟道晶体管中的沟槽的上角部分中的阈值电压，以及引入p型杂质，从而消除由于杂质在热处理期间的扩散而引起的阈值电压降低， 处理半导体衬底。 在p沟道晶体管中，通过舍入氧化来增加沟槽上角部分中的阈值电压，从而抵消由于将p型第一杂质引入沟槽的两个上角部而导致的阈值电压降低。

公开(公告)号：US06342440B1

公开(公告)日：2002-01-29

申请号：US09518246

申请日：2000-03-03

申请人： Kazuhiro Sasada ,  Yasunori Inoue ,  Shinichi Tanimoto ,  Atsuhiro Nishida ,  Yoshikazu Ibara

发明人： Kazuhiro Sasada ,  Yasunori Inoue ,  Shinichi Tanimoto ,  Atsuhiro Nishida ,  Yoshikazu Ibara

IPC分类号： H01L21425

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/665

摘要： A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an impurity region is formed by selectively ion-implanting an impurity into the main surface of a semiconductor substrate. The impurity region is activated by performing a high-temperature heat treatment. The semiconductor device is recovered from crystal defects resulting from the high-temperature heat treatment by performing a low-temperature heat treatment after performing the high-temperature heat treatment. According to this manufacturing method, the semiconductor device is recovered from the crystal defects resulting from the ion implantation by the high-temperature heat treatment, and recovered from the crystal defects resulting from the high-temperature heat treatment by the low-temperature heat treatment. Thus, increase of a leakage current caused by the crystal defects resulting from the high-temperature heat treatment can be effectively prevented.

摘要翻译： 获得能够抑制由高温热处理引起的漏电流增加的半导体装置的制造方法。 在该制造方法中，通过选择性地将杂质离子注入到半导体衬底的主表面中来形成杂质区。 通过进行高温热处理来激活杂质区域。 通过在进行高温热处理后进行低温热处理，从高温热处理得到的晶体缺陷中回收半导体装置。 根据该制造方法，通过高温热处理从离子注入产生的晶体缺陷中回收半导体器件，并且通过低温热处理从高温热处理引起的晶体缺陷中回收。 因此，可以有效地防止由高温热处理引起的晶体缺陷引起的漏电流的增加。

公开(公告)号：US08410557B2

公开(公告)日：2013-04-02

申请号：US12486062

申请日：2009-06-17

申请人： Haruki Yoneda ,  Kazuhiro Sasada

发明人： Haruki Yoneda ,  Kazuhiro Sasada

IPC分类号： H01L29/66

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased.

摘要翻译： 在源极层下方的N型体层下方，在元件隔离绝缘膜下方，在N型外延层中形成P型漂移层。 该P型漂移层在漏极层下方比元件隔离绝缘膜下方浅，并且从元件隔离绝缘膜下面逐渐浅到N型体层与N型体层的底部接触。 由于P型漂移层因此在宽范围内扩散，所以从N型体层到漏极层形成宽电流路径，并且电流驱动能力增强，漏极击穿电压也增加。

公开(公告)号：US08319281B2

公开(公告)日：2012-11-27

申请号：US11965536

申请日：2007-12-27

申请人： Yoshikazu Yamaoka ,  Satoru Shimada ,  Kazunori Fujita ,  Kazuhiro Sasada

发明人： Yoshikazu Yamaoka ,  Satoru Shimada ,  Kazunori Fujita ,  Kazuhiro Sasada

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.

摘要翻译： 可以获得能够在抑制绝缘膜的介电强度电压降低的同时抑制制造工艺的复杂化的半导体器件。 该半导体器件包括沟槽部分，形成在沟槽部分的表面上的绝缘膜，栅极电极和源极杂质区域，其中栅电极的与绝缘膜接触的部分的上端分别位于 在与半导体衬底的表面相对于绝缘膜引入的杂质的范围相同或更深的位置处，以形成源极杂质区域和源极杂质区域的下表面之上。

公开(公告)号：US20060170007A1

公开(公告)日：2006-08-03

申请号：US11340571

申请日：2006-01-27

申请人： Yoshinari Ichihashi ,  Ryu Shimizu ,  Kazuhiro Sasada

发明人： Yoshinari Ichihashi ,  Ryu Shimizu ,  Kazuhiro Sasada

IPC分类号： H01L29/768

CPC分类号： H01L31/02162 ,  H01L27/14623 ,  H01L27/14812 ,  H01L27/1485

摘要： A solid-state image sensor capable of suppressing color mixture while suppressing increase of load capacitances of transfer gates and a short circuit between two adjacent transfer gates is provided. This solid-state image sensor comprises a plurality of transfer gates and a shielding material line blocking light incident from above a prescribed pixel upon another pixel adjacent to the prescribed pixel. The shielding material line has a downward projecting portion on a region corresponding to at least one transfer gate entering an ON-state in photoreception.

摘要翻译： 提供一种能够抑制混色的同时抑制传输门的负载电容的增加和两个相邻的传输门之间的短路的固态图像传感器。 该固态图像传感器包括多个传输门和屏蔽材料线，该屏蔽材料线阻挡从与规定像素相邻的另一像素上的规定像素上方入射的光。 屏蔽材料线在对应于在光接收中进入导通状态的至少一个传输栅极的区域上具有向下突出部分。