公开(公告)号：US5949706A

公开(公告)日：1999-09-07

申请号：US236914

申请日：1999-01-26

Applicant: Ko-Min Chang ,  Bruce L. Morton ,  Clinton C. K. Kuo ,  Keith E. Witek ,  Kent J. Cooper

Inventor： Ko-Min Chang ,  Bruce L. Morton ,  Clinton C. K. Kuo ,  Keith E. Witek ,  Kent J. Cooper

IPC: G11C7/12 ,  G11C8/08 ,  G11C11/404 ,  G11C11/412 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  G11C11/00 ,  H01L27/11

CPC classification number: H01L27/10873 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0433 ,  G11C7/12 ,  G11C8/08 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/108 ,  H01L27/10891 ,  Y10S257/903

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract translation: 存储电路和形成方法使用传输门（24）作为选择栅极。 传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。 晶体管（28和30）并联电连接。 传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降 传输门。 此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

公开(公告)号：US5898619A

公开(公告)日：1999-04-27

申请号：US242993

申请日：1994-05-16

Applicant: Ko-Min Chang ,  Bruce L. Morton ,  Clinton C. K. Kuo ,  Keith E. Witek ,  Kent J. Cooper

Inventor： Ko-Min Chang ,  Bruce L. Morton ,  Clinton C. K. Kuo ,  Keith E. Witek ,  Kent J. Cooper

IPC: G11C7/12 ,  G11C8/08 ,  G11C11/404 ,  G11C11/412 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  G11C11/22 ,  G11C11/24

CPC classification number: H01L27/10873 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0433 ,  G11C7/12 ,  G11C8/08 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/108 ,  H01L27/10891 ,  Y10S257/903

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract translation: 存储电路和形成方法使用传输门（24）作为选择栅极。 传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。 晶体管（28和30）并联电连接。 传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降 传输门。 此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

公开(公告)号：US5554870A

公开(公告)日：1996-09-10

申请号：US510329

申请日：1995-08-02

Applicant: Jon T. Fitch ,  Suresh Venkatesan ,  Keith E. Witek

Inventor： Jon T. Fitch ,  Suresh Venkatesan ,  Keith E. Witek

IPC: H01L27/11 ,  H01L21/265 ,  H01L21/70

CPC classification number: H01L27/1104 ,  H01L27/1108 ,  H01L29/66666 ,  H01L29/7827

Abstract: An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodiment of the invention, all six transistors of an SRAM cell can be formed in single crystal material for improved device characteristics and increased cell density. Utilization of various combinations of vertical and horizontal devices permits a large degree of vertical integration within semiconductor devices.

Abstract translation: 集成电路（10）具有诸如晶体管（71）的垂直器件，其通过从衬底（12）和垂直器件外延生长的诸如晶体管（73,75）的水平器件外延生长形成。 根据本发明的一个实施例，SRAM单元的所有六个晶体管可以形成在单晶材料中，以改善器件特性和增加的单元密度。 使用垂直和水平装置的各种组合允许半导体器件内的大量垂直整合。

公开(公告)号：US5414289A

公开(公告)日：1995-05-09

申请号：US150328

申请日：1993-11-09

Applicant: Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek

Inventor： Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

CPC classification number: H01L27/10876 ,  H01L21/823487 ,  H01L27/10808 ,  H01L27/10823 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

Abstract translation: 垂直晶体管（10）具有用作控制电极或栅电极的基板（12）和控制电极导电层（18）。 侧壁电介质层（22）横向邻近控制电极导电层（18）形成并且覆盖在衬底（12）上。 导电层（18）至少部分地围绕沟道区域（30）。 在器件开口内形成垂直导电区域，其中导电区域的底部是第一电流电极（28）。 垂直导电区域的中间部分是沟道区域（30）。 垂直导电区域的顶部是第二电流电极（34）。

公开(公告)号：US5324683A

公开(公告)日：1994-06-28

申请号：US70613

申请日：1993-06-02

Applicant: Jon T. Fitch ,  Papu Maniar ,  Keith E. Witek ,  Jerry Gelatos ,  Reza Moazzami ,  Sergio A. Ajuria

Inventor： Jon T. Fitch ,  Papu Maniar ,  Keith E. Witek ,  Jerry Gelatos ,  Reza Moazzami ,  Sergio A. Ajuria

IPC: G01P15/08 ,  H01L21/768 ,  H01L23/482 ,  H01L21/76

CPC classification number: G01P15/0802 ,  H01L21/7682 ,  H01L23/4821 ,  H01L2924/0002 ,  Y10S148/073

Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Abstract translation: 一种用于形成覆盖在基底层（12）上的空气区域或空气桥的方法。 空气区域（20a，20b，28a和48）形成在基底层（12）上，以提供相邻导电层的改进的介电隔离，提供空气隔离的导电互连和/或形成许多其它微结构或微器件。 通过选择性地去除牺牲隔离物（16a和16b）或通过选择性地除去牺牲层（28,40）来形成空气区域（20a，20b，28a和48）。 空气区域（20a，20b，28a和48）通过选择性生长过程或通过非保形沉积技术被密封，封闭或隔离。 空气区域（20a，20b，28a和48）可以在任何压力，气体浓度或加工条件（即温度等）下形成。 空气区域（20a，20b，28a和48）可以形成在集成电路内的任何级别。

公开(公告)号：US5308782A

公开(公告)日：1994-05-03

申请号：US966643

申请日：1992-10-26

Applicant: Carlos A. Mazure ,  Jon T. Fitch ,  James D. Hayden ,  Keith E. Witek

Inventor： Carlos A. Mazure ,  Jon T. Fitch ,  James D. Hayden ,  Keith E. Witek

IPC: H01L27/00 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/70

CPC classification number: H01L29/66666 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/7834

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

Abstract translation: 形成具有基板（12）的半导体存储器件。 在衬底（12）内形成扩散（14）。 形成第一垂直晶体管堆叠（122）。 形成第二垂直晶体管堆叠（124）。 第一垂直晶体管堆叠（122）具有位于晶体管（104）下面的晶体管（100）。 第二垂直晶体管堆叠（124）具有位于晶体管（106）下方的晶体管（102）。 晶体管（100和104）串联连接，晶体管（102和106）串联连接。 在优选形式中，晶体管（100和102）电连接作为用于半导体存储器件的锁存晶体管，并且晶体管（106和104）作为传输晶体管连接。 两个垂直堆叠（126和128）形成用于半导体存储器件的电互连（118和120）和电阻器件（134和138）。

公开(公告)号：US5886382A

公开(公告)日：1999-03-23

申请号：US897254

申请日：1997-07-18

Applicant: Keith E. Witek

Inventor： Keith E. Witek

IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/11 ,  H01L21/70

CPC classification number: H01L29/66666 ,  H01L27/088 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1112 ,  H01L29/78657

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract translation: 用于形成沟槽晶体管结构的方法开始于通过外延生长处理在衬底（10）中形成掩埋层（12和16）和掺杂阱（22）。 然后将沟槽区域（24）蚀刻到衬底（10）中以暴露层（12）。 导电侧壁间隔件（28）形成在沟槽（24）内作为栅电极。 隔离物（28）将位于邻近沟槽（24）的第一半部分的第一晶体管（12,28,32）和邻近沟槽（24）的第二半部分定位的第二晶体管（12,28,34）。 区域（12）是公共电极，其中第一和第二晶体管的沟道区域以串联方式耦合通过区域（12）。

公开(公告)号：US5705409A

公开(公告)日：1998-01-06

申请号：US535397

申请日：1995-09-28

Applicant: Keith E. Witek

Inventor： Keith E. Witek

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L27/1104 ,  H01L29/66666 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/78657

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract translation: 用于形成沟槽晶体管结构的方法开始于通过外延生长处理在衬底（10）中形成掩埋层（12和16）和掺杂阱（22）。 然后将沟槽区域（24）蚀刻到衬底（10）中以暴露层（12）。 导电侧壁间隔件（28）形成在沟槽（24）内作为栅电极。 隔离物（28）将位于邻近沟槽（24）的第一半部分的第一晶体管（12,28,32）和邻近沟槽（24）的第二半部分定位的第二晶体管（12,28,34）。 区域（12）是公共电极，其中第一和第二晶体管的沟道区域以串联方式耦合通过区域（12）。

公开(公告)号：US5324673A

公开(公告)日：1994-06-28

申请号：US979073

申请日：1992-11-19

Applicant: Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek

Inventor： Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66666 ,  H01L21/28525 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/6675 ,  H01L29/7827

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

Abstract translation: 用于形成垂直晶体管（10）的方法通过提供衬底（12）开始。 形成在衬底（12）上方的导电层（16）。 通过选择性生长，外延生长，原位掺杂和/或离子注入之一，分别形成第一电流电极（26），第二电流电极（30）和沟道区（28）。 栅极电极或控制电极（34）横向邻近沟道区（28）形成。 使用选择性/外延生长步骤将导电层（16）连接到控制电极（34），并形成可靠且没有电流短路至电流电极（26和30）的控制电极互连。 晶体管（10）可以垂直堆叠以形成紧凑的反相器电路。

公开(公告)号：US5256588A

公开(公告)日：1993-10-26

申请号：US856411

申请日：1992-03-23

Applicant: Keith E. Witek ,  Carlos A. Mazure ,  Jon T. Fitch

Inventor： Keith E. Witek ,  Carlos A. Mazure ,  Jon T. Fitch

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10864 ,  H01L27/10841

Abstract: A method for forming a transistor and a capacitor to provide, in one form, a DRAM cell (10). The capacitor of cell (10) is formed within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric.

Abstract translation: 一种用于形成晶体管和电容器的方法，以一种形式提供DRAM单元（10）。 电池（10）的电容器形成在衬底（12）内。 电容器具有第一电容器电极（16）和第二电容器电极（20）。 电介质层（18）形成为电极间电容器电介质。 第一晶体管电流电极（36）被形成为覆盖并电连接到第一电容器电极（16）。 沟道区（38）形成在第一晶体管电流电极（36）的上方。 第二晶体管电流电极（40）形成在沟道区域（38）的上方。 导电层（30）横向邻近沟道区（38）形成，并通过电介质层（22和28）与衬底（12）隔离。 导电层（30）用作晶体管的栅电极，并且侧壁电介质（34）用作栅极电介质。