公开(公告)号：US07279997B2

公开(公告)日：2007-10-09

申请号：US11250994

申请日：2005-10-14

申请人： Sriram S. Kalpat ,  Leo Mathew ,  Mohamed S. Moosa ,  Michael A. Sadd ,  Hector Sanchez

发明人： Sriram S. Kalpat ,  Leo Mathew ,  Mohamed S. Moosa ,  Michael A. Sadd ,  Hector Sanchez

IPC分类号： H03L7/099

CPC分类号： H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

摘要： A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

公开(公告)号：US07612619B2

公开(公告)日：2009-11-03

申请号：US11387595

申请日：2006-03-23

申请人： Mohamed S. Moosa ,  Leo Mathew ,  Sriram S. Kalpat

发明人： Mohamed S. Moosa ,  Leo Mathew ,  Sriram S. Kalpat

IPC分类号： H03L7/00

CPC分类号： H03D13/00

摘要： A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.

摘要翻译： 公开了一种用于相位检测的装置和方法。 该装置包括相位差模块，该相位差模块基于数据信号和参考信号之间的相位差提供相位差信号。 相位差信号被提供给器件的多栅极鳍型场效应晶体管（多栅极FinFET）的第一栅极。 多栅极FinFET晶体管的第二栅极接收提供相位检测阈值的偏置信号。 基于相位差信号和偏置信号，在FinFET电流电极的一个或两个处提供相位调整信号。

公开(公告)号：US07439791B2

公开(公告)日：2008-10-21

申请号：US11344511

申请日：2006-01-31

申请人： Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

发明人： Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

IPC分类号： H01L35/00

CPC分类号： H03K17/145 ,  H01L29/785 ,  H03K17/687

摘要： A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate FinFET) transistor of a functional block. A second gate of the multigate FinFET transistor receives a control signal to control its operation within the functional block. In this configuration the first gate of the multigate FinFET transistor can be used for temperature compensation while the second gate is used for functional operation of the transistor. Specific embodiments of the present disclosure will be better understood with respect to the figures.

摘要翻译： 公开了一种用于电子设备的温度补偿的装置和方法。 该装置包括具有温度传感器的温度偏差控制器。 基于来自温度传感器的信号的偏置信号被提供给功能块的多鳍栅极场效应晶体管（多栅极FinFET）晶体管的第一栅极。 多栅极FinFET晶体管的第二栅极接收控制信号以控制其在功能块内的操作。 在该配置中，多栅极FinFET晶体管的第一栅极可用于温度补偿，而第二栅极用于晶体管的功能操作。 将更好地理解本发明的具体实施方式。

公开(公告)号：US07215268B1

公开(公告)日：2007-05-08

申请号：US11250993

申请日：2005-10-14

申请人： Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

发明人： Mohamed S. Moosa ,  Sriram S. Kalpat ,  Leo Mathew

IPC分类号： H03M1/00

CPC分类号： H03M1/361 ,  H01L27/0886 ,  H01L27/1211 ,  H03M1/745

摘要： An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.

摘要翻译： 提供了包括提供多个数字输出信号的多个独立的栅极场效应晶体管（MIGFET）的模数转换器。 多个MIGFET的每个MIGFET可以具有用于接收模拟信号的第一栅极，用于偏置的第二栅极和用于从多个数字输出信号中提供数字输出信号的电流电极。 多个MIGFET的每个MIGFET可以具有体宽度，多个MIGFET之间唯一的沟道长度的组合，以产生多个MIGFET中唯一的阈值电压。 还提供了包括多个MIGFET的数模转换器。

公开(公告)号：US08043888B2

公开(公告)日：2011-10-25

申请号：US12016733

申请日：2008-01-18

申请人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC分类号： H01L21/44

CPC分类号： H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

摘要翻译： 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

公开(公告)号：US20100227475A1

公开(公告)日：2010-09-09

申请号：US12784984

申请日：2010-05-21

申请人： Leo Mathew ,  Dharmesh Jawarani

发明人： Leo Mathew ,  Dharmesh Jawarani

IPC分类号： H01L21/44

CPC分类号： H01L21/26506 ,  H01L31/022425 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/0312 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/068 ,  H01L31/1864 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

摘要翻译： 形成电子器件的方法可以包括通过电化学工艺在包括半导体材料的衬底的侧面上形成金属层。 该方法还可以包括在距离侧面一定距离处将分离增强物质引入衬底中，并且将半导体层和金属层与衬底分离，其中半导体层是衬底的一部分。 在一个具体的实施方案中，分离增强物质可以结合到金属层中并移动到基底中，并且在具体实施方案中，可以将分离增强物质注入到基底中。 在另一个实施例中，可以使用这两种技术。 在另一实施例中，可以执行双面处理。

公开(公告)号：US07709303B2

公开(公告)日：2010-05-04

申请号：US11328668

申请日：2006-01-10

申请人： James D. Burnett ,  Leo Mathew ,  Byoung W. Min

发明人： James D. Burnett ,  Leo Mathew ,  Byoung W. Min

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

摘要翻译： 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US07432122B2

公开(公告)日：2008-10-07

申请号：US11327686

申请日：2006-01-06

申请人： Leo Mathew ,  Michael G. Khazhinsky

发明人： Leo Mathew ,  Michael G. Khazhinsky

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L27/0811 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/785

摘要： An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

摘要翻译： 电子设备可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。 与结点隔开并相邻的第一导电构件可连接到第一信号线。 与结点间隔开并与其相邻的第二导电构件可以电连接到第二信号线并与第一导电构件电绝缘。 结二极管结构可以包括p-n或p-i-n结。 还描述了用于形成电子设备的过程。

公开(公告)号：US07301741B2

公开(公告)日：2007-11-27

申请号：US11130873

申请日：2005-05-17

申请人： Michael G. Khazhinsky ,  Leo Mathew

发明人： Michael G. Khazhinsky ,  Leo Mathew

IPC分类号： H02H3/22

CPC分类号： H01L27/0251 ,  H01L27/0292 ,  H01L29/7855

摘要： A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled between the first (112) and second (114) power supply voltage rails, and first and second gates. The ESD event detector circuit (138) is coupled between the first (112) and second (114) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first (112) and second (114) power supply voltage rails, the ESD event detector circuit (138) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET (128) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET (128) conductive with relatively high conductivity.

摘要翻译： 轨道钳位电路（100）包括第一和第二电源电压轨道，多个独立的栅极场效应晶体管（MIGFET）（128）和ESD事件检测器电路（138）。 MIGFET（128）具有耦合在第一（112）和第二（114）电源电压轨道之间的源极/漏极路径，以及第一和第二栅极。 ESD事件检测器电路（138）耦合在第一（112）和第二（114）电源电压轨道之间，并且具有分别耦合到MIGFET的第一和第二栅极的第一和第二输出端子。 响应于第一（112）和第二（114）电源电压轨道之间的静电放电（ESD）事件，ESD事件检测器电路（138）向第二栅极提供电压以降低MIGFET的绝对阈值电压 （128），同时向第一栅极提供高于绝对阈值电压的电压，从而使MIGFET（128）具有较高导电性的导电性。

公开(公告)号：US20070181946A1

公开(公告)日：2007-08-09

申请号：US11349875

申请日：2006-02-08

申请人： Leo Mathew ,  Lixin Ge ,  Surya Veeraraghavan

发明人： Leo Mathew ,  Lixin Ge ,  Surya Veeraraghavan

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L29/785

摘要： A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

摘要翻译： 一种用于制造半导体器件的方法包括图案化覆盖在绝缘体层上的半导体层，以产生第一有源区和第二有源区，其中第一有源区具有与第二有源区不同的高度，并且其中至少 所述第一有源区的一部分具有第一导电类型，并且所述第二有源区的至少一部分具有与所述半导体器件的至少沟道区中的所述第一导电类型不同的第二导电类型。 该方法还包括在第一有源区和第二有源区的至少一部分上形成栅极结构。 该方法还包括去除半导体器件的一侧上的第二有源区的一部分。