公开(公告)号：US07098700B2

公开(公告)日：2006-08-29

申请号：US10886850

申请日：2004-07-08

Applicant: Nanci Martinez ,  Seth L. Everton ,  Erick M. Hirata ,  Lloyd F. Linder

Inventor： Nanci Martinez ,  Seth L. Everton ,  Erick M. Hirata ,  Lloyd F. Linder

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K19/01812 ,  H03K17/662

Abstract: An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Abstract translation: 输出驱动程序 新颖的输出驱动器包括用于接收输入信号并根据其在输出节点处产生输出信号的第一电路，用于向输出节点施加可变电流的第二电路和用于控制变量的幅度的第三电路 电流根据输入信号。 在说明性实施例中，第三电路适于根据输入信号产生控制电流，并且第二电路包括适于接收控制电流的电流镜，并将控制电流的缩放版本输出到输出节点。

公开(公告)号：US07088148B2

公开(公告)日：2006-08-08

申请号：US10863561

申请日：2004-06-08

Applicant: Don C. Devendorf ,  Lloyd F. Linder ,  Kelvin T. Tran

Inventor： Don C. Devendorf ,  Lloyd F. Linder ,  Kelvin T. Tran

IPC: G11C27/02

CPC classification number: G11C27/02

Abstract: A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.

Abstract translation: 一种采样和保持电路，包括用于接收输入信号的第一装置; 第二装置，用于响应于控制信号采样和保持信号; 以及当电路从轨道切换到保持或保持跟踪并且用于保持集电极发射极电压恒定在输入晶体管时，最小化输入晶体管的基极电流的变化的第三布置。 公开了一种通过将电流镜中的一个晶体管的电压保持恒定来提高二极管连接晶体管的电流镜的动态电流精度的装置。 公开了另一种用于将集电极保持到中间晶体管的发射极电压恒定的结构，从而提高增益精度和线性度。 在一个实施例中，添加虚拟支路以将输出电压与在从轨道到保持的转变时中间晶体管导通时发生的开关瞬变隔离。

公开(公告)号：US06717450B1

公开(公告)日：2004-04-06

申请号：US10144175

申请日：2002-05-13

Applicant: Lloyd F. Linder

Inventor： Lloyd F. Linder

IPC: H03K508

CPC classification number: G01R31/2834

Abstract: An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the current source and the current sink; and a control circuit for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as a voltage difference between a fixed reference voltage and a pin output voltage of a device under test.

Abstract translation: 用于测试集成电路的自动测试设备的有源负载电路。 有源负载电路包括电流源; 电流槽 电流开关电路具有分别连接到电流源和电流吸收器的电流源和电流汇点; 以及控制电路，用于以限制被测设备的固定参考电压和引脚输出电压之间的电压差的振幅和相同极性的差分电压来控制电流开关电路。

公开(公告)号：US06559530B2

公开(公告)日：2003-05-06

申请号：US09956402

申请日：2001-09-19

Applicant: David H. Hinzel ,  Charles L. Goldsmith ,  Lloyd F. Linder

Inventor： David H. Hinzel ,  Charles L. Goldsmith ,  Lloyd F. Linder

IPC: H01L2306

CPC classification number: B81B7/007 ,  B81B7/0006 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2924/10158

Abstract: A method of integrating MEMS devices with non-MEMS circuitry requires fabricating non-MEMS devices on a substrate in a conventional fashion. A thick dielectric layer is deposited on the completed devices, and the MEMS devices fabricated on the dielectric layer. Vias through the dielectric layer interconnect the MEMS devices to the non-MEMS electronics. The interposed dielectric layer allows the common substrate to have characteristics that best suit the non-MEMS components, without degrading the MEMS performance. Another approach involves bonding together two separate wafers—one for the MEMS devices and one for non-MEMS electronics. A package lid, having filled vias formed therethrough, is bonded to the MEMS wafer, sealing the MEMS devices within. The non-MEMS wafer is mounted to the lid, with the vias effecting the necessary interconnections between the two wafers. This enables the MEMS devices and the non-MEMS electronics to function as a single IC, while retaining the established processes associated with each component type.

Abstract translation: 将MEMS器件与非MEMS电路集成的方法需要以常规方式在衬底上制造非MEMS器件。 在完成的器件上沉积厚的介电层，并且在介电层上制造MEMS器件。 通过介电层的通孔将MEMS器件互连到非MEMS电子器件。 插入的电介质层允许公共衬底具有最适合于非MEMS组件的特性，而不降低MEMS性能。 另一种方法包括将两个单独的晶片结合在一起，一个用于MEMS器件，一个用于非MEMS电子器件。 具有通过其形成的填充通孔的封装盖结合到MEMS晶片上，密封MEMS器件内部。 非MEMS晶片安装到盖上，其中通孔在两个晶片之间实现必要的互连。 这使得MEMS器件和非MEMS电子器件能够用作单个IC，同时保持与每个部件类型相关联的已建立的工艺。

公开(公告)号：US06552343B1

公开(公告)日：2003-04-22

申请号：US09574123

申请日：2000-05-18

Applicant: Lloyd F. Linder ,  Alan E. Reamon

Inventor： Lloyd F. Linder ,  Alan E. Reamon

IPC: G01J500

CPC classification number: H01L27/14649

Abstract: A unit cell including a substrate; an active circuit disposed on the substrate; and an arrangement disposed on the substrate for routing a plurality of conductors thereover. In the illustrative implementation, the routing arrangement includes first, second and third ground planes disposed on the substrate, a first layer of conductors disposed between the first and second planes, and a second layer of conductors disposed between the second and the third planes. Each cell is adapted to connect to a device such as a detector. The inventive unit cell enables an improved focal plane array design with a smaller unit cell supporting smaller detector sizes. Smaller detector pitch allows higher density detector arrays. The inventive fan-out approach allows for complicated circuitry to be located outside the array. This permits the utilization of more sophisticated analog signed processing, such as a multiple sample approach. Multiple sampling results in a much more accurate digital Gaussian curvefit, which increases the range and intensity accuracy of readout electronics.

Abstract translation: 包括基板的晶胞; 设置在基板上的有源电路; 以及布置在所述基板上用于在其上布置多个导体的布置。 在说明性实施例中，路由布置包括设置在基板上的第一，第二和第三接地平面，布置在第一和第二平面之间的第一导体层和设置在第二和第三平面之间的第二导体层。 每个单元适于连接到诸如检测器的设备。 本发明的单元电池能够实现改进的焦平面阵列设计，其具有支持较小探测器尺寸的较小单元电池。 更小的检测器间距允许更高密度的检测器阵列。 本发明的扇出方法允许复杂的电路位于阵列外部。 这允许利用更复杂的模拟签名处理，例如多样本方法。 多次采样导致更准确的数字高斯曲线拟合，这增加了读出电子器件的范围和强度精度。

公开(公告)号：US06404228B1

公开(公告)日：2002-06-11

申请号：US09005411

申请日：1998-01-09

Applicant: Ralph T. Luna ,  Lloyd F. Linder ,  Erick M. Hirata

Inventor： Ralph T. Luna ,  Lloyd F. Linder ,  Erick M. Hirata

IPC: H03K190175

CPC classification number: H03K19/01806 ,  H03K19/01837 ,  H03K19/0826

Abstract: An apparatus for selectably converting emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL) signals to negative complimentary metal oxide semiconductor (NCMOS) signals is disclosed. The apparatus uses an input level shifter, a secondary level shifter, and an output buffer to convert the ECL and PECL differential signals to single-ended signals. The apparatus also includes a disable output function for disabling the output of the output buffer. The apparatus may be integrated multiple times on a substrate containing NCMOS circuitry, thereby allowing the NCMOS circuitry to be driven by differential signals. Alternatively, the present invention may be integrated multiple times onto a single substrate to create a dedicated universal translator.

Abstract translation: 公开了一种用于将发射极耦合逻辑（ECL）和正发射极耦合逻辑（PECL）信号可选择地转换为负互补金属氧化物半导体（NCMOS）信号的装置。 该装置使用输入电平移位器，次级电平移位器和输出缓冲器来将ECL和PECL差分信号转换为单端信号。 该装置还包括用于禁止输出缓冲器的输出的禁用输出功能。 该装置可以在包含NCMOS电路的基板上多次集成，从而允许NCMOS电路由差分信号驱动。 或者，本发明可以多次集成到单个基板上以创建专用通用转换器。

公开(公告)号：US6157224A

公开(公告)日：2000-12-05

申请号：US219759

申请日：1998-12-23

Applicant: Lloyd F. Linder

Inventor： Lloyd F. Linder

IPC: G01R31/28 ,  G01R31/319 ,  H03K19/003 ,  H03K19/013 ,  H03K19/018 ,  H03B1/00

CPC classification number: H03K19/01837 ,  G01R31/31924 ,  H03K19/00376 ,  H03K19/01806

Abstract: An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

Abstract translation: 改进的高速PIN驱动器集成电路和架构。 PIN驱动电路的结构在有源模式下不依赖于正常工作时的晶体管钳位，并且在抑制模式或主动模式下不需要高反向基极 - 发射极击穿电压，这与高速时的高速性能直接相反 针对CMOS，TTL，ECL电平兼容性的PIN电压偏移。 特别地，PIN驱动器电路始终是有源线性电路，并且始终保护任何晶体管的反向基极 - 发射极电压，并且不需要线或或钳位晶体管。 该架构使用复制偏移来消除禁止模式下的PIN驱动器的电流，这是在禁止模式下在PIN处产生的漏电流的自动测试设备的要求未被校准。 使用电流镜像电路，求和装置和缓冲电路来实现复制偏移，该电路在PIN驱动器电路的活动模式中产生电压副本。 本发明中使用的复制偏移方案跟踪温度和过程，并提供改进的高速电路，而不需要在禁止模式下校准泄漏电流。

公开(公告)号：US5859569A

公开(公告)日：1999-01-12

申请号：US843200

申请日：1997-04-14

Applicant: Hieu M. Le ,  Lloyd F. Linder ,  Erick M. Hirata ,  Benjamin Felder ,  Roger N. Kosaka ,  Donald G. McMullin ,  Kelvin T. Tran

Inventor： Hieu M. Le ,  Lloyd F. Linder ,  Erick M. Hirata ,  Benjamin Felder ,  Roger N. Kosaka ,  Donald G. McMullin ,  Kelvin T. Tran

IPC: H03F1/52 ,  H03F3/30 ,  H02H7/20 ,  H03M1/12

CPC classification number: H03F3/3076 ,  H03F1/52

Abstract: A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.

Abstract translation: 当差分输入超过安全阈值电平时，电流转向电路将偏置电流从差分电流求和放大器的前端转移，从而防止放大器的输出级过载。 转向前端的偏置电流也会关闭放大器前端的晶体管，从而保护前端免受过大输入信号造成的损坏。

公开(公告)号：US5581213A

公开(公告)日：1996-12-03

申请号：US479284

申请日：1995-06-07

Applicant: Lloyd F. Linder ,  Don C. Devendorf ,  Bruno W. Garlepp

Inventor： Lloyd F. Linder ,  Don C. Devendorf ,  Bruno W. Garlepp

IPC: H03G1/00 ,  H03G3/12

CPC classification number: H03G1/0088

Abstract: A non-attenuating automatic variable gain amplifier (VGA) circuit includes an operational amplifier (op amp) with a feedback resistor connected between its output and inverting input terminals. A variable gain setting resistance circuit having a variable resistance is the gain setting resistor positioned between the op amp's inverting input and a low voltage supply. By varying the resistance of the variable resistance circuit, the gain of the VGA circuit can be manipulated without requiring attenuation of the input signal. A resistance setting control for the variable resistance circuit can operate open loop, fed back from the amplifier output, or fed forward from the amplifier input.

Abstract translation: 非衰减自动可变增益放大器（VGA）电路包括运算放大器（运算放大器），反相电阻连接在其输出和反相输入端子之间。 具有可变电阻的可变增益设置电阻电路是位于运算放大器的反相输入和低电压电源之间的增益设置电阻。 通过改变可变电阻电路的电阻，可以在不需要衰减输入信号的情况下操纵VGA电路的增益。 可变电阻电路的电阻设置控制可以操作开路，从放大器输出反馈或从放大器输入端向前馈。

公开(公告)号：US5410274A

公开(公告)日：1995-04-25

申请号：US210269

申请日：1994-03-17

Applicant: Dwight D. Birdsall ,  Phillip L. Elliott ,  Lloyd F. Linder ,  Kelvin T. Tran ,  Donald G. McMullin

Inventor： Dwight D. Birdsall ,  Phillip L. Elliott ,  Lloyd F. Linder ,  Kelvin T. Tran ,  Donald G. McMullin

IPC: H03F3/26 ,  H03F3/30 ,  H03F3/45

CPC classification number: H03F3/3081 ,  H03F3/26 ,  H03F3/3067

Abstract: First and second current feedback transconductance amplifiers (102,104) each have a high impedance voltage input, a low impedance current input and a pair of push-pull current outputs. In a single-ended configuration, an input signal is applied to the voltage input of the first transconductance amplifier (102) and the push-pull outputs of the both transconductance amplifiers are connected through a current mirror (136,138) to a node (134) where the current outputs are summed. The node current is integrated by a capacitor (174) to produce a voltage which is amplified by a transimpedance amplifier (190) to produce an output voltage which is fed back to the voltage input of the second transconductance amplifier (104). The current inputs of the transconductance amplifiers (102,104) are interconnected by a resistor (132). The high impedance voltage inputs produce common-mode cancellation of distortion in the transconductance amplifiers (102,104) and low input shot noise. In a differential configuration, differential input signals are applied to the voltage inputs of transconductance amplifiers (260,262), and a separate transimpedance amplifier (292,316) and current mirror (278,280) (302,304) is provided for each transconductance amplifier (260,262). A common-mode feedback circuit (352) controls the common-mode output voltages of the transimpedance amplifiers (292,316) to ground. Switch means (402,404,406,408,410,412) may be added to selectively ground the voltage inputs of the transconductance amplifiers (260,262) and disable their input stages by disconnecting their power supplies (VCC,VEE).

Abstract translation: 第一和第二电流反向跨导放大器（102,104）各自具有高阻抗电压输入，低阻抗电流输入和一对推挽电流输出。 在单端配置中，输入信号被施加到第一跨导放大器（102）的电压输入，并且两个跨导放大器的推挽输出通过电流镜（136,138）连接到节点（134） 其中当前输出相加。 节点电流由电容器（174）积分以产生被跨阻放大器（190）放大的电压，以产生反馈到第二跨导放大器（104）的电压输入端的输出电压。 跨导放大器（102,104）的电流输入通过电阻器（132）互连。 高阻抗电压输入产生跨导放大器（102,104）中的失真的共模消除和低输入散射噪声。 在差分配置中，差分输入信号被施加到跨导放大器（260,262）的电压输入端，并为每个跨导放大器（260,262）提供单独的跨阻抗放大器（292,316）和电流镜（278,308）（302,304）。 共模反馈电路（352）控制跨阻放大器（292,316）的共模输出电压接地。 可以添加开关装置（402,404,406,408,410,412）以有选择地接地跨导放大器（260,262）的电压输入，并且通过断开它们的电源（VCC，VEE）来禁用它们的输入级。