公开(公告)号：US20100270622A1

公开(公告)日：2010-10-28

申请号：US12831815

申请日：2010-07-07

申请人： Mahalingam NANDAKUMAR ,  Wayne A. BATHER ,  Narendra Singh MEHTA ,  Lahir Shaik ADAM

发明人： Mahalingam NANDAKUMAR ,  Wayne A. BATHER ,  Narendra Singh MEHTA ,  Lahir Shaik ADAM

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.

摘要翻译： 本发明提供一种半导体器件的制造方法以及半导体器件。 除了其他步骤之外，该方法可以包括在衬底上形成栅极结构，以及在栅极结构的侧壁附近形成应变诱导侧壁间隔，所述应变诱导侧壁被配置为在栅极结构下方的沟道区域中引入应变。

公开(公告)号：US07678637B2

公开(公告)日：2010-03-16

申请号：US12209270

申请日：2008-09-12

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US07638402B2

公开(公告)日：2009-12-29

申请号：US11728928

申请日：2007-03-27

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

摘要翻译： 在形成晶体管时实现侧壁间隔器回拉方案。 除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。 较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。 该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。 这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

公开(公告)号：US20090170277A1

公开(公告)日：2009-07-02

申请号：US12345414

申请日：2008-12-29

申请人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

发明人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC分类号： H01L21/764 ,  H01L21/302

CPC分类号： H01L21/76254 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139

摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

摘要翻译： 提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。 提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。 一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。 除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。 第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

公开(公告)号：US20080160708A1

公开(公告)日：2008-07-03

申请号：US11728928

申请日：2007-03-27

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

摘要翻译： 在形成晶体管时实现侧壁间隔器回拉方案。 除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。 较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。 该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。 这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

公开(公告)号：US20060246645A1

公开(公告)日：2006-11-02

申请号：US11457569

申请日：2006-07-14

申请人： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

发明人： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7836 ,  H01L29/6659

摘要： A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.

摘要翻译： 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。

公开(公告)号：US20060024873A1

公开(公告)日：2006-02-02

申请号：US10902657

申请日：2004-07-28

申请人： Mahalingam Nandakumar ,  Haowen Bu

发明人： Mahalingam Nandakumar ,  Haowen Bu

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.

摘要翻译： 本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。 源极/漏极区170具有位于它们之间的沟道区175。 第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

公开(公告)号：US20050170576A1

公开(公告)日：2005-08-04

申请号：US11066756

申请日：2005-02-23

申请人： Mahalingam Nandakumar

发明人： Mahalingam Nandakumar

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6653 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

摘要翻译： 一种制造晶体管（10）的方法包括使用第一侧壁（42）和（43）作为掩模形成源区和漏区（46）和（47），并形成深覆盖源和漏区（54）和（ 56）使用第二侧壁（50）和（51）作为掩模，所述第二侧壁（50）和（51）包括所述第一侧壁（42）和（43）的至少一部分。

公开(公告)号：US20050156236A1

公开(公告)日：2005-07-21

申请号：US10979693

申请日：2004-11-01

申请人： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

发明人： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/7836 ,  H01L29/6659

摘要： A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of an separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.

摘要翻译： 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。

公开(公告)号：US20050118770A1

公开(公告)日：2005-06-02

申请号：US10956864

申请日：2004-10-01

申请人： Mahalingam Nandakumar ,  Shaoping Tang ,  Haowen Bu

发明人： Mahalingam Nandakumar ,  Shaoping Tang ,  Haowen Bu

IPC分类号： H01L21/30 ,  H01L21/324 ,  H01L21/336 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain regions in the substrate (210). The method further includes annealing the substrate containing the at least a portion of source/drain regions in the presence of hydrogen, and forming an interlevel dielectric layer over the substrate (210) having previously been annealed in the presence of hydrogen.

摘要翻译： 本发明提供一种半导体器件的制造方法及其制造方法。 除了其他步骤之外，制造半导体器件的方法包括在衬底（210）上形成栅极结构（230）并且形成衬底（210）中的源极/漏极区域的至少一部分。 该方法还包括在存在氢的情况下对包含至少一部分源极/漏极区的衬底进行退火，以及在预先在氢气存在下预先退火的衬底（210）上形成层间电介质层。