公开(公告)号：US5242852A

公开(公告)日：1993-09-07

申请号：US944883

申请日：1992-09-11

申请人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

发明人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L28/40 ,  Y10S438/908

摘要： In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.

摘要翻译： 在以堆叠式存储单元型制造DRAM的方法中，蚀刻第一绝缘膜时，每个位线的边缘部分被露出，裸露的边缘部分被从开口蚀刻并且开口的内周面被 第二绝缘膜。 还公开了一种方法，其中第二绝缘膜和第三绝缘膜和第二导电膜堆叠在第一绝缘膜上，形成第二导电膜，并且第二导电膜和第一导电膜被部分蚀刻，由此第一绝缘膜的未蚀刻部分 导电膜用作电荷存储电极的电极平面。

公开(公告)号：US5275972A

公开(公告)日：1994-01-04

申请号：US930485

申请日：1992-08-14

申请人： Hisashi Ogawa ,  Yasushi Naito ,  Masanori Fukumoto

发明人： Hisashi Ogawa ,  Yasushi Naito ,  Masanori Fukumoto

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  Y10S438/97

摘要： A fabrication method for a semiconductor integrated circuits which permits the self-aligned formation of contact windows without causing shorts or breaks in the interconnecting lines in the device is provided. After forming gate electrodes and source/drain regions of transistors on a semiconductor substrate, an etch-stop layer and a BPSG film are successively deposited over the gate electrodes and the source/drain regions. After a resist having a contact window pattern is formed on the BPSG film, an isotropic dry etching using a microwave plasma is performed to etch the BPSG film. According to the isotropic dry etching, the laterally etching rate in the BPSG film can be controlled by adjusting the RF power, and a silicon dioxide film can be used as the etch stop layer. After the BPSG flow process, the etch stop layer on the contact region is etched away to form contact windows.

摘要翻译： 提供一种用于半导体集成电路的制造方法，其允许接触窗口的自对准形成而不引起装置中的互连线中的短路或断裂。 在半导体衬底上形成晶体管的栅电极和源极/漏极区之后，在栅电极和源极/漏极区上依次沉积蚀刻停止层和BPSG膜。 在BPSG膜上形成具有接触窗图案的抗蚀剂之后，使用微波等离子体进行各向同性的干蚀刻来蚀刻BPSG膜。 根据各向同性干蚀刻，可以通过调节RF功率来控制BPSG膜中的横向蚀刻速率，并且可以使用二氧化硅膜作为蚀刻停止层。 在BPSG流动过程之后，蚀刻掉接触区域上的蚀刻停止层以形成接触窗口。

公开(公告)号：US5128274A

公开(公告)日：1992-07-07

申请号：US721186

申请日：1991-06-26

申请人： Toshiki Yabu ,  Masanori Fukumoto ,  Yasushi Naito

发明人： Toshiki Yabu ,  Masanori Fukumoto ,  Yasushi Naito

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76221 ,  H01L21/32 ,  H01L27/105 ,  Y10S438/981

摘要： There are provided semiconductor devices including a semiconductor substrate having a surface divided into a first and second regions, a plurality of active regions formed on the substrate, and a local-oxidized (LOCOS) insulating film formed on the substrate as an isolation region for electrical isolation of the active regions from each other. The LOCOS insulating film is thicker in the first region than in the second region, or the LOCOS insulating film has a difference in level based on the thickness change in the vicinity of the boundary between the first and second regions. Also provided are various methods for producing such semiconductor devices.

摘要翻译： 提供了半导体器件，其包括具有分为第一和第二区域的表面的半导体衬底，形成在衬底上的多个有源区域和形成在衬底上的局部氧化（LOCOS）绝缘膜，作为电气隔离区域 活性区域彼此隔离。 LOCOS绝缘膜在第一区域比第二区域厚，或者LOCOS绝缘膜基于第一和第二区域之间的边界附近的厚度变化而具有不同的水平。 还提供了用于制造这种半导体器件的各种方法。

公开(公告)号：US20070108530A1

公开(公告)日：2007-05-17

申请号：US11543223

申请日：2006-10-05

申请人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

发明人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on the sides of the gate electrode and an insulating film formed to cover the gate electrode and the source/drain regions to cause stress strain in part of the region below the gate electrode.

摘要翻译： 半导体器件包括形成在半导体区域的区域中的MIS晶体管。 MIS晶体管包括形成在该区域上的栅极绝缘膜，形成在栅极绝缘膜上并完全硅化金属的栅极电极，形成在栅极侧面上的部分区域中的源极/漏极区域和形成的绝缘膜 以覆盖栅极电极和源极/漏极区域，以在栅电极下方的部分区域引起应力应变。

公开(公告)号：US5856219A

公开(公告)日：1999-01-05

申请号：US912686

申请日：1997-08-18

申请人： Yasushi Naito ,  Yutaka Ito ,  Yuichi Hirofuji

发明人： Yasushi Naito ,  Yutaka Ito ,  Yuichi Hirofuji

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/1052 ,  H01L27/10873

摘要： The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions

摘要翻译： 本发明涉及用于以自对准方式在字线之间形成源极/漏极接触的高密度DRAM制造技术，其中外围晶体管的源极区域和漏极区域之间的偏移长度保持在足够的值。 在形成栅电极（即字线）之后，沉积足够薄而不能阻挡字线之间限定的空间的第一绝缘层。 源极/漏极接触被蚀刻为第一绝缘层较厚的深度，以形成由多晶硅制成的引出电极。 沉积第二绝缘层，直到获得用于确定偏移长度的间隔物厚度（即第二绝缘层的膜厚度和第一绝缘层的膜厚度之和）。 第一绝缘层和第二绝缘层被回蚀一段对应于第二绝缘层的膜厚度与第一绝缘层的膜厚之和的距离，使得间隔物（即，绝缘层的残留物）留在 栅电极的侧壁。 执行高级杂质的注入以形成外围晶体管的重掺杂源极和漏极区域。 在保持重掺杂源极和漏极区域的偏移长度的同时使单元内自对准接触成为可能

公开(公告)号：US5459101A

公开(公告)日：1995-10-17

申请号：US266218

申请日：1994-06-27

申请人： Toyokazu Fujii ,  Yasushi Naito

发明人： Toyokazu Fujii ,  Yasushi Naito

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/265 ,  H01L21/283

CPC分类号： H01L21/76889 ,  H01L21/28061 ,  H01L21/823842 ,  H01L23/53271 ,  H01L2924/0002

摘要： A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed on the insulating film. The polysilicon layer includes a p-type region having p-type impurities diffused therein and an n-type region having n-type impurities diffused therein. The p-type impurities are implanted into the silicide layer in order to have a substantially uniform concentration over the entire portion thereof, so that the p-type impurities in the p-type region of the polysilicon layer do not diffuse into the silicide film by a post heat treatment.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘膜和在绝缘膜上形成的包括多晶硅层和硅化物层的多晶硅膜。 多晶硅层包括在其中扩散有p型杂质的p型区域和在其中扩散n型杂质的n型区域。 将p型杂质注入到硅化物层中以在其整个部分上具有基本上均匀的浓度，使得多晶硅层的p型区域中的p型杂质不会通过以下方式扩散到硅化物膜中： 后热处理。

公开(公告)号：US20140151709A1

公开(公告)日：2014-06-05

申请号：US14236361

申请日：2011-08-03

申请人： Seiji Nishiyama ,  Yasushi Naito

发明人： Seiji Nishiyama ,  Yasushi Naito

IPC分类号： H01L27/32

CPC分类号： H01L27/3246 ,  G02B5/201 ,  H01L27/3211 ,  H01L27/3218 ,  H01L27/3262 ,  H01L51/0031

摘要： Provided is a display panel having a plurality of pixels arranged in a matrix of rows and columns. Each of the pixels is composed of a plurality of first sub-pixels emitting light of different colors. Each of the first sub-pixels is composed of a plurality of second sub-pixels emitting light of the same color. Each of the second sub-pixels includes: a first electrode; a second electrode above the first electrode; and a light-emitting layer between the first electrode and the second electrode.

摘要翻译： 提供了具有排列成行和列的矩阵的多个像素的显示面板。 每个像素由发射不同颜色的光的多个第一子像素组成。 每个第一子像素由发射相同颜色的光的多个第二子像素构成。 每个第二子像素包括：第一电极; 在所述第一电极上方的第二电极; 以及在第一电极和第二电极之间的发光层。

公开(公告)号：US20130310289A1

公开(公告)日：2013-11-21

申请号：US13818329

申请日：2011-08-19

申请人： Kazuhiro Umehara ,  Kenji Yamamoto ,  Masaki Maruyama ,  Yasushi Naito ,  Satoru Yoshida

发明人： Kazuhiro Umehara ,  Kenji Yamamoto ,  Masaki Maruyama ,  Yasushi Naito ,  Satoru Yoshida

IPC分类号： C10M169/04

CPC分类号： C10M169/04 ,  C10M135/18 ,  C10M2203/1025 ,  C10M2203/1085 ,  C10M2205/0285 ,  C10M2207/026 ,  C10M2207/262 ,  C10M2207/289 ,  C10M2209/084 ,  C10M2215/06 ,  C10M2215/064 ,  C10M2215/28 ,  C10M2219/068 ,  C10M2223/045 ,  C10N2210/06 ,  C10N2220/022 ,  C10N2230/02 ,  C10N2230/04 ,  C10N2230/08 ,  C10N2230/10 ,  C10N2230/42 ,  C10N2230/54 ,  C10N2240/10 ,  C10N2240/102 ,  C10N2240/104 ,  C10N2210/02

摘要： Provided is a lubricating oil composition for an internal combustion engine, including: an organic molybdenum compound as a component (A); a base oil having a kinematic viscosity at 100° C. of 25 mm2/s or more as a component (B); and a base oil having a kinematic viscosity at 100° C. of less than 12.5 mm2/s as a component (C), in which the composition has a kinematic viscosity at 100° C. of 5 mm2/s to 12.5 mm2/s and a phosphorus content of 800 ppm or less.

摘要翻译： 提供一种用于内燃机的润滑油组合物，其包括：作为组分（A）的有机钼化合物; 作为组分（B），在100℃下的运动粘度为25mm 2 / s以上的基油; 和作为组分（C）的在100℃下的运动粘度低于12.5mm 2 / s的基础油，其中组合物在100℃下的运动粘度为5mm 2 / s至12.5mm 2 / s 磷含量为800ppm以下。

公开(公告)号：US07037733B2

公开(公告)日：2006-05-02

申请号：US10343762

申请日：2002-07-01

申请人： Satoshi Shibata ,  Junji Hirase ,  Tatsuo Sugiyama ,  Emi Kanasaki ,  Fumitoshi Kawase ,  Yasushi Naito

发明人： Satoshi Shibata ,  Junji Hirase ,  Tatsuo Sugiyama ,  Emi Kanasaki ,  Fumitoshi Kawase ,  Yasushi Naito

IPC分类号： H01L21/66 ,  G01N25/00 ,  G01J5/00

CPC分类号： G01J5/0003

摘要： When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ε, such as a DPS film, is formed on the reverse face of the substrate 10.

摘要翻译： 当在衬底10的退火处理期间测量衬底10的反面上的发射率ε时，由用于形成插头15A的第一DPS膜15，例如用于形成插头15A的第一DPS膜15的材料制成的膜，第二 用于形成用于形成电容器上电极20A的电容器下电极17A和第三DPS膜20的DPS膜17形成在基板10的顶面上。另一方面，没有由材料制成的膜 在基板10的背面上形成改变发射率ε（例如DPS膜）。

公开(公告)号：US5314848A

公开(公告)日：1994-05-24

申请号：US764846

申请日：1991-09-24

申请人： Takatoshi Yasui ,  Chiaki Kudo ,  Ichiro Nakao ,  Toyokazu Fujii ,  Yuka Terai ,  Shinichi Imai ,  Hiroshi Yamamoto ,  Yasushi Naito

发明人： Takatoshi Yasui ,  Chiaki Kudo ,  Ichiro Nakao ,  Toyokazu Fujii ,  Yuka Terai ,  Shinichi Imai ,  Hiroshi Yamamoto ,  Yasushi Naito

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/00 ,  H01L21/02 ,  H01L21/324 ,  H01L21/477

CPC分类号： H01L21/76819 ,  H01L21/3105 ,  Y10S148/133 ,  Y10S438/909

摘要： Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.

摘要翻译： 描述了一种用于制造半导体器件的方法，其包括根据预定温度分布以预定间距对安装在船上的半导体衬底进行加热和冷却的热处理工艺，以便通过回流绝缘膜来平坦化每个半导体衬底的表面 含有杂质，例如在基板上形成的BPSG膜。 在热处理过程中，设定影响绝缘膜中含有杂质的晶粒或颗粒形成的控制因素之一，以防止杂质在热处理过程中产生晶粒或颗粒。 还公开了通过扩大安装的基板的间距来防止颗粒或颗粒的产生的方法。