公开(公告)号：US5804874A

公开(公告)日：1998-09-08

申请号：US811150

申请日：1997-03-04

申请人： Min Cheol An ,  Do Soo Jeong

发明人： Min Cheol An ,  Do Soo Jeong

IPC分类号： H01L25/18 ,  H01L23/04 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L24/83 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181

摘要： A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device. The leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected. An insulating adhesive film is interposed between the upper semiconductor chip and the inner leads of the lower lead frame.

摘要翻译： 一种堆叠式芯片封装，包括上部，其包括上半导体芯片，所述上半导体芯片具有设置在所述半导体芯片的有源表面的中心区域上的多个电极接合焊盘; 上引线框架，其具有在所述上半导体芯片的有源表面上延伸并且与所述半导体芯片的电极接合焊盘电互连的引线; 下部包括具有设置在半导体芯片的有源表面的中心区域上的多个电极接合焊盘的下半导体芯片; 下引线框架具有在下半导体芯片的有源表面上延伸的内引线，其电连接到下半导体芯片的电极接合焊盘，以及外引线，用于将堆叠的芯片封装电连接到外部电路器件。 上引线框架的引线形成为直接接触下引线框架的内引线的顶表面，使得上和下部件可以电互连。 在上半导体芯片和下引线框架的内引线之间插入绝缘粘合膜。

公开(公告)号：US6104095A

公开(公告)日：2000-08-15

申请号：US87903

申请日：1998-05-01

申请人： Bo Hyun Shin ,  Min Cheol An

发明人： Bo Hyun Shin ,  Min Cheol An

IPC分类号： H01L23/28 ,  H01L23/12 ,  H01L23/13 ,  H01L23/31 ,  H01L27/10 ,  H05K1/16 ,  A01L23/28 ,  A01L23/02 ,  A01L23/48 ,  A01L23/495 ,  A01L23/52

CPC分类号： H01L23/13 ,  H01L23/3121 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/1579 ,  H01L2924/181

摘要： A printed circuit board (PCB) for use in chip-on-board (COB) packages reduces failures due to warping of the COB packages. The PCB includes a board body having a upper surface and a lower surface, a chip bonding area on the upper surface for attaching a semiconductor device, and a plurality of conductors in a circuit pattern on the upper surface outside the chip bonding area, for electrical connection to the semiconductor device using a plurality of bonding wires. An encapsulation region encloses the chip bonding area, the bonding wires, a portion of the plurality of conductors, and a portion of the upper surface. The board includes external contacts on the lower surface for electrical connections to an external electrical appliance, and via holes through the board body for electrically connecting the plurality of conductors in the circuit pattern to the external contacts. A plurality of volume-adjusting regions, on the upper surface outside the chip bonding area and inside the encapsulation region, adjust a volume of a molding compound in the final package.

摘要翻译： 用于板载（COB）封装的印刷电路板（PCB）减少了由于COB封装翘曲引起的故障。 PCB包括具有上表面和下表面的板体，用于附接半导体器件的上表面上的芯片接合区域和在芯片接合区域的上表面上的电路图案中的多个导体，用于电气 使用多个接合线连接到半导体器件。 封装区域包围芯片接合区域，接合线，多个导体的一部分以及上表面的一部分。 该电路板包括在下表面上用于与外部电气设备的电连接的外部触点，以及穿过电路板主体的通孔，用于将电路图案中的多个导体电连接到外部触点。 在芯片接合区域的外表面和封装区域内的上表面上的多个体积调节区域调节最终封装中的模塑料的体积。

公开(公告)号：US6028774A

公开(公告)日：2000-02-22

申请号：US81098

申请日：1998-05-19

申请人： Bo Hyun Shin ,  Jung Hwan Cuun ,  Min Cheol An

发明人： Bo Hyun Shin ,  Jung Hwan Cuun ,  Min Cheol An

IPC分类号： B42D15/10 ,  G06K19/00 ,  G06K19/07 ,  G06K19/077 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H01L23/13

CPC分类号： G06K19/07745 ,  H01L23/49855 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/142 ,  H05K1/182

摘要： A base card improves the mounting reliability of a COB package particularly when the package has molding by-products such as epoxy burrs or molding flashes. The base card has a COB package receiving part made up of first and second sections. The receiving part is stepped so that the sections thereof have shapes that are complementary to that of and for receiving a peripheral portion of the printed circuit board of the COB package and the package body the COB package, respectively. The second section has a bevel at the transition of the first section into the second section. This bevel helps define a space in which the by-products are accommodated when the COB package is mounted to the base card. Further, the second section of the COB package receiving part may define an opening in the bottom surface of the base card. This opening also prevents damage to the base card by preventing the need for the bottom of the package body to bear against the bottom of the base card when the COB package is mounted to the base card.

摘要翻译： 基卡提高了COB封装的安装可靠性，特别是当封装具有成型副产品如环氧树脂毛刺或成型闪光时。 基卡具有由第一和第二部分组成的COB包装容纳部。 接收部分是台阶状的，使得它们的部分分别与COB封装的印刷电路板的周边部分和COB封装的封装体互补的形状。 第二部分在第一部分到第二部分的过渡处具有斜面。 当COB封装安装到基卡时，该斜面有助于定义容纳副产品的空间。 此外，COB封装容纳部件的第二部分可以限定底卡底面的开口。 当COB封装安装到基卡上时，该开口也防止了对基卡的损坏，防止了封装体的底部承受基座的底部。

公开(公告)号：US5744827A

公开(公告)日：1998-04-28

申请号：US753532

申请日：1996-11-26

申请人： Do Soo Jeong ,  Min Cheol An ,  Seung Ho Ahn ,  Hyeon Jo Jeong ,  Ki Won Choi

发明人： Do Soo Jeong ,  Min Cheol An ,  Seung Ho Ahn ,  Hyeon Jo Jeong ,  Ki Won Choi

IPC分类号： H01L25/18 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H01L27/00 ,  H01L23/48 ,  H01L23/02 ,  H01L25/04

CPC分类号： H01L23/49551 ,  H01L23/4951 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511

摘要： A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

摘要翻译： 一种三维堆叠封装装置，可以实现堆叠的单个封装装置的垂直电互连，而无需成本增加或额外复杂的处理步骤。 三维封装器件包括多个单独的半导体器件，每个单独的半导体器件包括（1）半导体芯片，（2）用于封装半导体芯片的保护体，（3）引线框架，其包括内部引线部分， 所述半导体芯片包括在所述保护体内，所述外部引线部分与所述内部引线部分形成为单一主体，以及耦合引线部分，位于所述内引线部分和所述引线部分之间，并且具有从所述保护体向上露出的顶表面，以及 4）多个垂直互连元件，其附接到所述耦合引线部分的后表面并且从与所述耦合引线部分的暴露的顶表面相对的方向从所述保护体露出，由此所述多个单独的半导体器件 由耦合引线部分和垂直互连元件实现 并且三维堆叠封装器件与外部电路器件的电互连由最下半导体器件的外部引线部分实现。