公开(公告)号：US5407532A

公开(公告)日：1995-04-18

申请号：US146624

申请日：1993-10-29

Applicant: San-Chin Fang ,  Nadia Lifshitz

Inventor： San-Chin Fang ,  Nadia Lifshitz

IPC: H01L21/3213 ,  H01L21/60 ,  H01L21/8244 ,  H01L23/532 ,  H01L27/11 ,  H01L21/312

CPC classification number: H01L21/76897 ,  H01L21/32136 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Parallel metallization lines for a substrate of an electronic device, such as complementary bit (B and B) lines for an SRAM cell array, are formed by:forming a uniformly thick aluminum layer with an underlying and overlying dielectric oxide layer, the underlying oxide layer being located overlying the substrate,patterning the overlying oxide and the aluminum layers to form the aluminum bit line (B) with an overlying dielectric oxide layer on its top surface, typically by means of reactive ion etching,depositing a further dielectric oxide layer on the entire surface of the structure including the sidewalls of the aluminum bit line (B), andreactive ion etching the top surface of the oxide layer, whereby an oxide layer remains on the top and sidewall surfaces of the aluminum bit line (B) but not elsewhere.Subsequent forming of a second uniformly thick aluminum layer on the top surface of the structure that is being fabricated, followed by patterning this second aluminum layer, forms the complementary aluminum bit line (B).

Abstract translation: 用于电子器件的衬底的平行金属化线，例如用于SRAM单元阵列的互补位（B和＆amp; upbar＆B）线，通过：形成均匀厚的铝层，其具有下面和上面的电介质氧化物层，下面的氧化物 层叠位于衬底上方，图案化覆盖的氧化物和铝层，以形成铝位线（B），其上表面的电介质氧化物层通常通过反应离子蚀刻，将另外的电介质氧化物层沉积在 结构的整个表面包括铝位线（B）的侧壁，并且反应离子蚀刻氧化物层的顶表面，由此氧化层保留在铝位线（B）的顶壁和侧壁表面上，但是 不在别处 随后在正在制造的结构的顶表面上形成第二均匀厚的铝层，随后构图该第二铝层，形成互补的铝位线（＆amp;上升＆B）。

公开(公告)号：US4333793A

公开(公告)日：1982-06-08

申请号：US199023

申请日：1980-10-20

Applicant: Nadia Lifshitz ,  Joseph M. Moran ,  David N. Wang

Inventor： Nadia Lifshitz ,  Joseph M. Moran ,  David N. Wang

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/312

Abstract: In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.

Abstract translation: 在VLSI器件制造工艺中，在下层（14）的干蚀刻期间，图案化的抗蚀剂层（16,18）的侵蚀可以显着地限制该工艺的高分辨率图案化能力。 如本文所述，保护性聚合物层（60,62）仅在蚀刻下层（14）时形成并保持在抗蚀剂材料（16,18）上。 由此实现了高蚀刻选择性。 因此，在制造工艺中可以使用非常薄的抗蚀剂层，从而使VLSI器件的非常高分辨率图案化变得可行。

公开(公告)号：US4450620A

公开(公告)日：1984-05-29

申请号：US468032

申请日：1983-02-18

Applicant: Ellis N. Fuls ,  Nadia Lifshitz ,  Sheila Vaidya

Inventor： Ellis N. Fuls ,  Nadia Lifshitz ,  Sheila Vaidya

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/43 ,  H01L21/74 ,  H01L21/265

CPC classification number: H01L21/32155 ,  H01L21/2257 ,  H01L21/28518 ,  H01L21/76889

Abstract: In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.

Abstract translation: 在MOS集成电路器件中，多层多晶硅/金属硅化物栅极级金属化结构被图案化以形成栅极和相关联的互连。 一些互连件被设计成与装置的单晶体体中的欧姆区域接触。 根据简化的制造过程，使用单个注入步骤来掺杂金属硅化物，同时掺杂身体的选定部分。 在随后的加热步骤期间，在体内形成源极，漏极和欧姆接触区域。 在相同的步骤中，金属硅化物中的掺杂剂扩散到多晶硅的下面的层中，并且以足以使多晶硅导电并在体内形成额外的欧姆接触区域的量直接在多晶硅下面的主体部分中扩散。

公开(公告)号：US4978915A

公开(公告)日：1990-12-18

申请号：US432947

申请日：1989-11-07

Applicant: John M. Andrews, Jr. ,  Nadia Lifshitz ,  Gerald Smolinsky

Inventor： John M. Andrews, Jr. ,  Nadia Lifshitz ,  Gerald Smolinsky

IPC: G01R31/01 ,  G01R31/26

CPC classification number: G01R31/016 ,  G01R31/2639

Abstract: The TVS method is a voltammetric method for detecting mobile ionic impurities in the dielectric layer of a MOS capacitor structure. Disclosed here is a method of semiconductor device fabrication involving a modified TVS method in which the voltage is changed in discrete steps rather than varied continuously, and charge, rather than induced current, is measured. The modified TVS method can be faster than conventional TVS, and calibration is unnecessary.

Abstract translation: TVS方法是用于检测MOS电容器结构的电介质层中的移动离子杂质的伏安法。 这里公开了一种半导体器件制造方法，其涉及改进的TVS方法，其中电压以离散步长改变而不是连续变化，并且测量电荷而不是感应电流。 改进的TVS方法可以比传统的TVS更快，并且校准是不必要的。

公开(公告)号：US5550397A

公开(公告)日：1996-08-27

申请号：US299855

申请日：1994-09-01

Applicant: Nadia Lifshitz ,  Serge Luryi

Inventor： Nadia Lifshitz ,  Serge Luryi

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/04 ,  H01L31/36

CPC classification number: H01L29/4983 ,  H01L29/4908

Abstract: The gate electrode of a polysilicon gate MOS transistor--the transistor having either a thin film polysilicon substrate or a bulk monocrystalline substrate--has a pair of contiguous regions: a heavily doped gate electrode region near the source, and a lightly doped gate electrode region near the drain. The gate electrode region near the drain is thus doped significantly more lightly, in order to reduce electric fields in the channel region in the neighborhood of the drain (and hence reduce field induced leakage currents) when voltages are applied to turn transistor OFF. At the same time, sufficient impurity doping is introduced into the gate electrode region near the source in order to enable the transistor to turn ON when other suitable voltages are applied.

Abstract translation: 多晶硅栅极MOS晶体管的栅电极 - 具有薄膜多晶硅衬底或大块单晶衬底的晶体管具有一对连续区域：靠近源极的重掺杂栅极电极区域和接近源极的轻掺杂栅电极区域 排水。 因此，漏极附近的栅极电极区域被更明显地掺杂，以便在施加电压以使晶体管截止时减小漏极附近的沟道区域中的电场（并因此减小场感应泄漏电流）。 同时，在源极附近的栅极电极区域中引入足够的杂质掺杂，以便在施加其它合适的电压时晶体管导通。

公开(公告)号：US5166091A

公开(公告)日：1992-11-24

申请号：US708970

申请日：1991-05-31

Applicant: Nadia Lifshitz ,  Ronald J. Schutz

Inventor： Nadia Lifshitz ,  Ronald J. Schutz

IPC: H01L27/12 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/822 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66765 ,  H01L21/32137 ,  H01L21/8221 ,  Y10S148/053 ,  Y10S148/122

Abstract: In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.

公开(公告)号：US5149672A

公开(公告)日：1992-09-22

申请号：US754361

申请日：1991-08-29

Applicant: Nadia Lifshitz ,  Ronald J. Schutz

Inventor： Nadia Lifshitz ,  Ronald J. Schutz

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  Y10S148/02

Abstract: For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 .mu.m and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Abstract translation: 对于具有严格设计规则的集成电路器件，定义源极和漏极的结通常通常比0.25μm更浅，并且通过具有大于1.1的纵横比的通孔制成。 与这样一个浅结的合适的电接触是相当困难的。 为了确保适当的接触，首先沉积诸如氮化钛的粘附阻挡层或钛和钨的合金。 然后在硅上原型沉积中产生自限制效应的条件下沉积钨。 另外，这些钨沉积条件被调整到较高而不是较低的沉积温度。 如果需要，随后沉积铝，完成接触。

公开(公告)号：US4938847A

公开(公告)日：1990-07-03

申请号：US395929

申请日：1989-08-18

Applicant: John M. Andrews, Jr. ,  Nadia Lifshitz ,  Gerald Smolinsky

Inventor： John M. Andrews, Jr. ,  Nadia Lifshitz ,  Gerald Smolinsky

IPC: G01N27/12 ,  H01L21/3105

CPC classification number: H01L21/3105 ,  G01N27/121

Abstract: Disclosed is a method of semiconductor device fabrication involving the detection of water in a dielectric layer that is part of the body of such device. At relatively high values of a voltage applied across the dielectric layer, water that is present in the dielectric decomposes and releases protons. Varying the applied voltage gives rise to a displacement current. The released protons contribute an ionic component to the displacement current. The ionic component is detected.

Abstract translation: 公开了一种半导体器件制造方法，其涉及在作为这种器件的主体的一部分的电介质层中的水的检测。 在施加在电介质层上的相对较高的电压值下，介电层中存在的水分解和释放质子。 改变施加电压会产生位移电流。 释放的质子对位移电流贡献离子成分。 检测离子成分。