CIRCUITRY AND APPARATUSES FOR MONITORING AND CONTROLLING A BATTERY AND CONFIGURABLE BATTERIES

    公开(公告)号:US20200059106A1

    公开(公告)日:2020-02-20

    申请号:US16543432

    申请日:2019-08-16

    IPC分类号: H02J7/00 B60L58/22 H01M10/48

    摘要: A battery management system having and configurable batteries are disclosed. The battery management system generally includes (a) one or more cell control units, each configured to control and/or balance a charge in a plurality of battery cells, and (b) a master controller in electrical communication with cell control unit(s). The cell control unit(s) as a whole include one or more switches, configured to be electrically connected to a first one of a plurality of battery cells, and a resistor, capacitor or inductor electrically (i) connected to one switch and (ii) connected or connectable to a second battery cell. The master controller is configured to open or close each switch. The configurable battery generally includes a plurality of battery cells and switches configured to connect or disconnect the battery cells in a configurable or predetermined manner.

    SHORT CIRCUIT REDUCTION IN A FERROELECTRIC MEMORY CELL COMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLE SUBSTRATE
    3.
    发明申请
    SHORT CIRCUIT REDUCTION IN A FERROELECTRIC MEMORY CELL COMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLE SUBSTRATE 有权
    在包含安装在柔性基板上的层叠的电介质存储单元中的短路电路减少

    公开(公告)号:US20140210026A1

    公开(公告)日:2014-07-31

    申请号:US14128011

    申请日:2011-06-27

    摘要: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer (11) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

    摘要翻译: 铁电存储器单元(1)和包括一个或多个这样的单元(1)的存储器件(100)。 铁电存储单元包括布置在柔性基板(3)上的层叠层(4)。 所述堆叠包括电活性部分(4a)和保护层(11),用于保护电活性部分免受划伤和磨损。 所述电活性部分包括底电极层(5)和顶电极层(9)和在所述电极之间的至少一个铁电存储材料层(7)。 该堆叠还包括布置在顶部电极层(9)和保护层(11)之间的缓冲层(13)。 缓冲层(13)适于至少部分地吸收出现在保护层(11)中的横向尺寸变化(&Dgr; L),从而防止所述尺寸变化(&Dgr; L)转移到电活性部件 4a),从而降低在电极之间发生短路的风险。

    Card-like memory unit with separate read/write unit
    4.
    发明授权
    Card-like memory unit with separate read/write unit 有权
    带有单独读/写单元的卡状存储单元

    公开(公告)号:US08184467B2

    公开(公告)日:2012-05-22

    申请号:US11917571

    申请日:2006-06-08

    IPC分类号: G11C11/22

    摘要: In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

    摘要翻译: 在非易失性电存储器系统中,存储单元和读/写单元被提供为物理上分离的单元。 存储器单元基于可以通过在存储器材料上施加电场而被设置为至少两种不同物理状态的存储器材料。 电极和/或触点被提供在存储器单元中或读/写单元中,并且触点至少总是设置在读/写单元中。 电极和触点以几何布置提供,其几何地限定存储器层中的一个或多个存储器单元。 在存储器单元和读/写单元之间建立物理接触关闭寻址的存储单元上的电路,从而可以实现读,写或擦除操作。 存储器单元的存储材料可以被偏振成两个可识别的偏振状态。

    Operating temperature optimization in a ferroelectric or electret memory
    6.
    发明授权
    Operating temperature optimization in a ferroelectric or electret memory 失效
    在铁电或驻极体记忆中的工作温度优化

    公开(公告)号:US07248524B2

    公开(公告)日:2007-07-24

    申请号:US11168375

    申请日:2005-06-29

    IPC分类号: G11C7/04

    摘要: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

    摘要翻译: 在包括至少一个可矩阵寻址的铁电或驻极体存储装置的数据存储装置的加热和温度控制系统中,在存储装置中提供焦耳加热装置,温度确定装置与控制器电路连接,并且控制器电路被连接 具有外部电源,由前者的焦炭控制,焦耳加热意味着实现选定的工作温度。 在用于操作加热和温度控制系统的方法中,确定存储器件的环境温度或即时温度并将其与设定的标称最佳温度进行比较,并且在用于建立应用的控制参数的预定义算法中使用这些温度之间的差异 的焦耳加热装置的功率,以在其寻址操作期间实现存储装置中的选定的工作温度。

    Method for performing write and read operations in a passive matrix memory, and apparatus for performing the method
    7.
    发明授权
    Method for performing write and read operations in a passive matrix memory, and apparatus for performing the method 有权
    在无源矩阵存储器中执行写入和读取操作的方法,以及用于执行该方法的装置

    公开(公告)号:US06606261B2

    公开(公告)日:2003-08-12

    申请号:US09899094

    申请日:2001-07-06

    IPC分类号: G11C1112

    CPC分类号: G11C11/22

    摘要: A method and apparatus for performing read and write operations in matrix-addressed memory array of memory cells is described. The memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular and electret or ferroelectric material, where a logical value stored in a memory cell is represented by an actual polarization state in the memory cell. The degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.

    摘要翻译: 描述了一种在存储器单元的矩阵寻址存储器阵列中执行读和写操作的方法和装置。 存储单元包括表现出极化剩磁的电可极化材料,特别是驻极体或铁电材料,其中存储在存储单元中的逻辑值由存储单元中的实际极化状态表示。 在每个读取和写入周期期间,可极化材料中的极化程度被限制在由控制读取和写入操作的电路装置定义的值,所述值范围从零到上限,对应于极化饱和度,并与 用于可靠地检测存储器单元的逻辑状态的预定标准。

    SHORT CIRCUIT REDUCTION IN AN ELECTRONIC COMPONENT COMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLE SUBSTRATE
    9.
    发明申请
    SHORT CIRCUIT REDUCTION IN AN ELECTRONIC COMPONENT COMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLE SUBSTRATE 有权
    在包含柔性基板上的堆叠层的电子元件中短路电路减少

    公开(公告)号:US20140216791A1

    公开(公告)日:2014-08-07

    申请号:US14128003

    申请日:2012-06-21

    IPC分类号: H05K1/16 H05K3/46 H05K1/02

    摘要: An electronic component (1) and an electronic device (100) comprising one or more such components (1). The electronic component (1) comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes. The stack further comprises a buffer layer (13), arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer (11) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

    摘要翻译: 电子部件(1)和包括一个或多个这样的部件(1)的电子设备(100)。 电子部件(1)包括布置在柔性基板(3)上的层(4)。 所述堆叠包括电活性部分(4a)和保护层(11),用于保护电活性部分免受划伤和磨损。 所述电活性部分包括底部电极层(5)和顶部电极层(9)以及所述电极之间的至少一个绝缘或半绝缘层(7)。 该堆叠还包括布置在顶部电极层(9)和保护层(11)之间的缓冲层(13)。 缓冲层(13)适于至少部分地吸收出现在保护层(11)中的横向尺寸变化(&Dgr; L),从而防止所述尺寸变化(&Dgr; L)转移到电活性部件 4a),从而降低在电极之间发生短路的风险。

    Method for reading a passive matrix-addressable device and a device for performing the method
    10.
    发明授权
    Method for reading a passive matrix-addressable device and a device for performing the method 有权
    用于读取无源矩阵寻址装置的方法和用于执行该方法的装置

    公开(公告)号:US06982895B2

    公开(公告)日:2006-01-03

    申请号:US10289419

    申请日:2002-11-07

    CPC分类号: G11C11/22

    摘要: A passive matrix-addressable device may include individually addressable cells of a polarizable material. The cells store data in one of two polarization states in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines. The cells are provided in or at the crossings between the word and bit lines and a voltage pulse protocol is used read and write data to cells. During reading, a word line is activated by applying voltage which relative to the potential on all crossing bit lines corresponds to the voltage Vs and data stored in the cells connected to this active word line are determined by detecting the charge values of the cells.

    摘要翻译: 无源矩阵寻址设备可以包括可极化材料的单独可寻址单元。 单元将数据存储在每个单元中的两个极化状态之一中,并且单元中的极化状态通过寻址形成字和位线的电极来写入和读取。 单元被提供在字和位线之间或之间的交叉点处,并且使用电压脉冲协议来将数据读取和写入单元。 在读取期间,通过施加相对于所有交叉位线上的电位对应于电压V S的电压来激活字线,并且通过检测来确定存储在连接到该有源字线的单元中的数据 电池的电荷值。