中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.011 seconds)

    Masking high-aspect aspect ratio structures
    2.
    发明申请
    Masking high-aspect aspect ratio structures 审中-公开
    掩盖高边宽高比结构

    公开(公告)号：US20080138581A1

    公开(公告)日：2008-06-12

    申请号：US11807763

    申请日：2007-05-29

    Applicant: Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher ,  Richard Normann

    Inventor： Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher ,  Richard Normann

    IPC: G03F7/00 ,  B32B3/00

    CPC classification number: G03F7/16 ,  Y10T428/24479

    Abstract: A method of masking high-aspect ratio structures on a wafer includes submerging the wafer in a resist material so that the high-aspect ratio structures are at least partially embedded within the resist material. The resist material is cured and further processing steps, such as for example oxygen plasma etching, are applied, for example to remove portions of the resist material and material from upper portions of the high-aspect ratio structures.

    Abstract translation: 屏蔽晶片上的高纵横比结构的方法包括将晶片浸没在抗蚀剂材料中，使得高纵横比结构至少部分地嵌入抗蚀剂材料内。 抗蚀剂材料被固化，并且施加进一步的加工步骤，例如氧等离子体蚀刻，例如从高纵横比结构的上部去除抗蚀剂材料和材料的部分。

    Neuroelectrode Coating and Associated Methods
    4.
    发明申请
    Neuroelectrode Coating and Associated Methods 审中-公开
    神经电极涂层及相关方法

    公开(公告)号：US20090246515A1

    公开(公告)日：2009-10-01

    申请号：US12334208

    申请日：2008-12-12

    Applicant: Sandeep Negi ,  Rajmohan Bhandari ,  Florian Solzbacher

    Inventor： Sandeep Negi ,  Rajmohan Bhandari ,  Florian Solzbacher

    IPC: C23C14/34 ,  C25F1/00 ,  B32B9/00

    CPC classification number: C23C14/0036 ,  A61B5/04011 ,  A61B2562/046 ,  A61N1/05 ,  C23C14/08 ,  C23C14/5846 ,  Y10T428/265

    Abstract: Micro-neuroelectrodes for use in stimulation of neurons can be formed having decreased impedance, increased charge storage capacity, and good durability. A method of coating a micro-neuroelectrode includes sputtering a film of iridium oxide on a surface of the micro-neuroelectrode. The sputtering can occur using pulse-DC conditions under reactive conditions that are sufficient to form a polycrystalline iridium oxide film that adheres to the surface of the micro-neuroelectrode. The deposited iridium oxide film can also be optionally activated to increase its charge storage capacity.

    Abstract translation: 可以形成用于刺激神经元的微神经电极，其具有降低的阻抗，增加的电荷存储容量和良好的耐久性。 包被微神经电极的方法包括在微神经电极的表面上溅射氧化铱膜。 溅射可以在足以形成粘附到微神经电极表面的多晶氧化铱膜的反应条件下使用脉冲 - 直流条件进行。 沉积的氧化铱膜也可以任选地被激活以增加其电荷存储容量。

    Methods for Wafer Scale Processing of Needle Array Devices
    6.
    发明申请
    Methods for Wafer Scale Processing of Needle Array Devices 审中-公开
    针阵器件晶圆尺寸加工方法

    公开(公告)号：US20090301994A1

    公开(公告)日：2009-12-10

    申请号：US12464691

    申请日：2009-05-12

    Applicant: Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher

    Inventor： Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher

    IPC: C23F1/02

    CPC classification number: B81C1/00111 ,  A61B5/04001 ,  A61B5/685 ,  A61B2562/125 ,  A61M2037/0053 ,  A61N1/0531 ,  A61N1/0543 ,  B81B2201/055 ,  B81B2207/056

    Abstract: Methods of fabricating needle arrays on a wafer scale include etching a wafer of columns and needles and coating the same with an electrically insulating material and exposing electrically conductive tips. This process can benefit from using a slow spin speed to distribute resist material across the wafer before etching and using a carrier wafer to support singulated arrays to allow full coverage of upper array surfaces with electrically insulating materials. These processes allow for efficient high volume production of high count microelectrode arrays with a high repeatability and accuracy.

    Abstract translation: 在晶片尺寸上制造针阵列的方法包括蚀刻柱和针的晶片，并用电绝缘材料涂覆其并暴露导电尖端。 该方法可以受益于在蚀刻之前使用缓慢旋转速度来分布抗蚀剂材料，并且使用载体晶片来支持单个阵列以允许用电绝缘材料完全覆盖上部阵列表面。 这些方法允许以高重复性和精度有效地大量生产高计数微电极阵列。

    Self-Aligning Latch-up Mechanism in Out of Plane Silicon Microelectrode Arrays
    9.
    发明申请
    Self-Aligning Latch-up Mechanism in Out of Plane Silicon Microelectrode Arrays 审中-公开
    平面硅微​​电极阵列中的自对准闩锁机制

    公开(公告)号：US20100010601A1

    公开(公告)日：2010-01-14

    申请号：US12350113

    申请日：2009-01-07

    Applicant: Sandeep Negi ,  Rajmohan Bhandari ,  Florian Solzbacher ,  Richard A. Normann

    Inventor： Sandeep Negi ,  Rajmohan Bhandari ,  Florian Solzbacher ,  Richard A. Normann

    IPC: A61N1/05 ,  H01L21/3205 ,  H01L21/304 ,  H01L21/306 ,  B32B43/00

    CPC classification number: A61N1/05 ,  A61B5/04001 ,  A61B5/685 ,  A61N1/0551 ,  A61N1/0558 ,  A61N1/37205 ,  B81B2201/13 ,  B81C3/008 ,  Y10T156/195

    Abstract: The present invention provides microelectrode array stabilizing devices and associated methods. A microelectrode array stabilizing device includes a first microelectrode array substrate having a plurality of first microelectrodes configured to penetrate tissue. A plurality of first interlocking structures are coupled to the first microelectrode array substrate, with each of the plurality of first interlocking structures including a first interlocking mechanism at a distal end. The device may further include a second microelectrode array substrate which optionally has a plurality of second microelectrodes configured to penetrate tissue. A plurality of second interlocking structures are coupled to the second microelectrode array substrate, each of the plurality of second interlocking structures including a second interlocking mechanism at a distal end. The second interlocking mechanism is complimentary to the first interlocking mechanism. The first microelectrode array and the second microelectrode array are configured to self-align and couple together with the first interlocking mechanism secured to the second interlocking mechanism.

    Abstract translation: 本发明提供微电极阵列稳定装置及相关方法。 微电极阵列稳定装置包括具有构造成穿透组织的多个第一微电极的第一微电极阵列基板。 多个第一互锁结构联接到第一微电极阵列基板，多个第一互锁结构中的每一个包括位于远端的第一互锁机构。 该装置还可以包括第二微电极阵列衬底，其可选地具有构造成穿透组织的多个第二微电极。 多个第二互锁结构联接到第二微电极阵列基板，多个第二互锁结构中的每一个在远端包括第二互锁机构。 第二互锁机构与第一互锁机构互补。 第一微电极阵列和第二微电极阵列被配置为与固定到第二互锁机构的第一互锁机构自对准和耦合在一起。

    Micro-Lens Arrays and Curved Surface Fabrication Techniques
    10.
    发明申请
    Micro-Lens Arrays and Curved Surface Fabrication Techniques 有权
    微镜阵列和曲面制作技术

    公开(公告)号：US20080297910A1

    公开(公告)日：2008-12-04

    申请号：US12129655

    申请日：2008-05-29

    Applicant: Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher

    Inventor： Rajmohan Bhandari ,  Sandeep Negi ,  Florian Solzbacher

    IPC: G02B3/00 ,  B29D11/00

    CPC classification number: B29D11/00596 ,  B29D11/00365 ,  G02B3/0025

    Abstract: A method of fabricating a sub-millimeter scale curved surface on a substrate (10) includes cutting a plurality of trenches (12) of varying depth into the substrate (10). The depth of the trenches (12) corresponds to a desired surface profile. The substrate (10) is etched to remove material left (16) between the trenches to form the curved surface.

    Abstract translation: 在衬底（10）上制造亚毫米级曲面的方法包括将不同深度的多个沟槽（12）切割成衬底（10）。 沟槽（12）的深度对应于所需的表面轮廓。 蚀刻衬底（10）以去除沟槽之间留下的材料（16）以形成弯曲表面。

Patent Agency Ranking