-
公开(公告)号：US20080277642A1
公开(公告)日：2008-11-13
申请号：US11814800
申请日：2006-01-19
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1691
摘要： A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure (210, 215) surrounded by the conductive electrode portions (200, 240) at its lateral sides, and is formed in a CMOS backend process. An alternative is to form the device coupled directly to other circuit parts without the electrodes. In each case, there is a line of PCM which has a constant diameter or cross section, formed with reduced dimensions by using a spacer as a hard mask. The first contact electrode and the second contact electrode are electrically connected by a “one dimensional” layer of the PCM. The contact resistance between the one-dimensional layer of PCM and the first contact electrode at the second contact electrode is lower than the resistance of a central or intervening portion of the line.
摘要翻译： 相变电阻器件具有相变材料（PCM），在该相变材料（PCM）中，相变发生在PCM内部，而不在与接触电极的界面处。 为了便于制造，PCM是由导电电极部分（200,240）在其侧面环绕的细长线结构（210,215），并且以CMOS后端工艺形成。 一种替代方案是形成直接连接到没有电极的其它电路部件的装置。 在每种情况下，存在具有恒定直径或横截面的PCM线，其通过使用间隔件作为硬掩模以减小的尺寸形成。 第一接触电极和第二接触电极通过PCM的“一维”层电连接。 PCM的一维层和第二接触电极处的第一接触电极之间的接触电阻低于线的中心部分或中间部分的电阻。
-
2.发明授权Method of manufacturing semiconductor devices each including a semiconductor body with a surface provided with a metallization having a Ti layer and a TiN layer 失效制造半导体器件的方法，每个半导体器件包括具有设置有具有Ti层和TiN层的金属化的表面的半导体本体
公开(公告)号：US5858183A
公开(公告)日：1999-01-12
申请号：US422687
申请日：1995-04-14
IPC分类号： C23C14/34 , C23C14/00 , C23C14/06 , C23C14/16 , C23C14/54 , H01J37/34 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768
CPC分类号： C23C14/0641 , C23C14/165 , H01L21/76843
摘要： A method of manufacturing semiconductor devices whereby first a Ti layer (8) and then a TiN layer (9) are deposited on slices of semiconductor material (20). The slices are placed on a support (30) one after the other in a deposition chamber (22), the support being positioned opposite a target of Ti (32) surrounded by an annular anode (31). Material is then sputtered off the target by means of a plasma (35) generated near the target. The plasma is generated in Ar during deposition of the Ti layer and in a gas mixture of Ar and N.sub.2 during deposition of the TiN layer. After the deposition of the TiN layer, before a next slice is placed in the chamber each time, the target is cleaned during an additional process step in that material is sputtered off the target by means of a plasma generated in Ar. The additional process step is ended the moment the target has regained a clean Ti surface again. It is achieved by this that an extra Ti layer comprising nitrogen is indeed deposited on the TiN layer during this additional process step, but that this is as thin as possible and accordingly contains as little free Ti as possible. Undesirable chemical reactions between free Ti and the conductive layers deposited on the layer comprising nitrogen are suppressed as much as possible thereby.
摘要翻译： 一种制造半导体器件的方法，其中首先在半导体材料（20）的切片上沉积Ti层（8），然后沉积TiN层（9）。 切片在沉积室（22）中一个接一个地放置在支撑件（30）上，支撑件与由环形阳极（31）包围的Ti（32）的靶相对。 然后通过在目标附近产生的等离子体（35）将材料溅射离开目标。 在沉积TiN层期间，在沉积Ti层期间和在Ar和N2的气体混合物中，Ar中产生等离子体。 在沉积TiN层之后，在每次将下一个切片放置在腔室中之前，在额外的工艺步骤中清洁靶材，其中材料通过在Ar中产生的等离子体溅射离开靶材。 额外的工艺步骤在目标已经重新获得清洁的Ti表面的时刻结束。 实现这一点，在该附加工艺步骤期间，在氮化钛层上确实沉积了包含氮的额外的Ti层，但是其尽可能薄，因此尽可能少地含有游离Ti。 游离Ti与沉积在包含氮的层上的导电层之间的不希望的化学反应被尽可能地抑制。
-
3.发明授权Method of manufacturing a semiconductor device whereby a layer containing aluminium is deposited on a surface of a semiconductor body 失效制造半导体器件的方法，由此在半导体本体的表面上沉积含有铝的层
公开(公告)号：US5266524A
公开(公告)日：1993-11-30
申请号：US947031
申请日：1992-09-17
IPC分类号： C23C14/14 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44 , C23C14/00
CPC分类号： H01L21/2855 , H01L21/76877 , Y10S148/158
摘要： A method of manufacturing a semiconductor device whereby a layer (3) containing aluminium is deposited by means of a sputter deposition process on a surface (1) of a semiconductor body (2) which is placed on a holder (21) in a reaction chamber (20). The semiconductor body (2) is cooled down to a temperature below 150 K. during the deposition process. A smooth, flat layer with a good step coverage is deposited in this way.
-
公开(公告)号：US08415226B2
公开(公告)日：2013-04-09
申请号：US13063782
申请日：2009-10-02
IPC分类号： H01L21/20
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/12 , H01L45/1675
摘要： A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ≧5 nm.
摘要翻译： 相变存储器单元，例如 线电池（2）及其制造，所述电池包括：两个电极（6,8）; 相变记忆材料（10）和电介质阻挡层（12）。 电介质势垒（12）被布置成提供电子隧穿，例如 Fowler-Nordheim隧道，到相变记忆材料（10）。 还可以提供由相变记忆材料制成的触点（15）。 电介质势垒（12）基本上是均匀的 基本均匀的厚度，例如 ≥5nm。
-
公开(公告)号：US08138768B2
公开(公告)日：2012-03-20
申请号：US12523840
申请日：2008-01-20
CPC分类号： H01L23/576 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has an inhomogeneous protective layer or coating over a circuit to be protected, and a sensing circuit (80) arranged to sense a first impedance of a part of the protective coating compared to a reference impedance (CO) located on the integrated circuit. The sensing circuit is able to measure a change in the first impedance, e.g. caused by tampering. The sensing circuit has an amplifier (OTA) having a feedback loop, such that the impedance being sensed is in the feedback loop. The sensing circuit can be incorporated in an oscillator circuit (OTA, Comp) so that the frequency depends on the impedance. Where the impedance is a capacitance, sensing electrodes adjacent to the protective layer or coating, form the capacitance. The electrodes can be arranged as selectable interdigitated comb structures, so that the protective layer or coating extends in between the teeth of the comb structures.
摘要翻译： 集成电路在要保护的电路上具有不均匀的保护层或涂层;以及感测电路（80），其布置成与位于集成电路上的参考阻抗（CO）相比感应保护涂层的一部分的第一阻抗 。 感测电路能够测量第一阻抗的变化，例如， 造成篡改。 感测电路具有具有反馈回路的放大器（OTA），使得被感测的阻抗处于反馈回路中。 感测电路可以结合在振荡器电路（OTA，Comp）中，使得频率取决于阻抗。 在阻抗为电容的地方，与保护层或涂层相邻的感应电极形成电容。 电极可以被布置为可选择的叉指梳状结构，使得保护层或涂层在梳结构的齿之间延伸。
-
6.发明授权Method of manufacturing a semiconductor device comprising a ferroelectric memory element 失效制造包括铁电存储元件的半导体器件的方法
公开(公告)号：US6140173A
公开(公告)日：2000-10-31
申请号：US25372
申请日：1998-02-18
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/43 , H01L29/788 , H01L29/792 , H01L29/12
CPC分类号： H01L27/11502
摘要： The invention relates to a semiconductor device comprising a semiconductor body (3) with a semiconductor element (1) with an electrically conducting region (5) on which a capacitor (2) forming a memory element is present with a lower electrode (11), an oxidic ferroelectric dielectric (12), and an upper electrode (13), which lower electrode (11) makes electrical contact with the conducting region (5) and comprises a layer with a conductive metal oxide (112) and a layer (111) comprising platinum. The layer with the conductive metal oxide (112) acts as an oxygen barrier during manufacture. The invention also relates to a method of manufacturing such a semiconductor device.According to the invention, the device is characterized in that the layer comprising platinum (111) contains more than 15 atom % of a metal capable of forming a conductive metal oxide, and in that the layer (112) with the conductive metal oxide is present between the layer (111) comprising platinum and the ferroelectric dielectric (12).A good electrical contact between the lower electrode (11) and the conducting region (5) after manufacture is achieved thereby.
摘要翻译： 本发明涉及一种半导体器件，包括具有半导体元件（1）的半导体本体（3），所述半导体元件（1）具有导电区域（5），在其上存在形成存储元件的电容器（2），并具有下电极（11） 氧化铁电介质（12）和上电极（13），所述下电极（11）与所述导电区域（5）电接触，并且包括具有导电金属氧化物（112）和层（111）的层， 包括铂。 具有导电金属氧化物（112）的层在制造期间用作氧阻隔层。 本发明还涉及一种制造这种半导体器件的方法。 根据本发明，该装置的特征在于，包含铂（111）的层含有大于15原子％的能够形成导电金属氧化物的金属，并且存在具有导电金属氧化物的层（112） 在包含铂的层（111）和铁电电介质（12）之间。 由此实现制造后的下部电极（11）与导电区域（5）之间的良好的电接触。
-
公开(公告)号：US07943509B2
公开(公告)日：2011-05-17
申请号：US12521982
申请日：2008-12-31
申请人： Roel Daamen , Robertus A. M. Wolters , Martinus P. M. Maas , Pascal Bancken , Julien M. M. Michelon
发明人： Roel Daamen , Robertus A. M. Wolters , Martinus P. M. Maas , Pascal Bancken , Julien M. M. Michelon
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L21/76849 , H01L21/76867 , H01L2221/1031
摘要： A damascene process is described using a copper fill process to fill a trench (12). The copper fill (20) is started with a deposited seed layer which includes (5) copper and titanium. Some titanium migrates to the surface during the copper fill process. The structure is annealed in a nitrogen atmosphere which creates a self-aligned TiN barrier (24) at the surface of the copper fill (20). Air gaps (26) may be created in the same annealing process. The process may be used to form a multilayer structure.
摘要翻译： 描述使用铜填充工艺填充沟槽（12）的镶嵌工艺。 铜填充物（20）由包括（5）铜和钛的沉积种子层开始。 在铜填充过程中，一些钛迁移到表面。 该结构在氮气氛中退火，在铜填充物（20）的表面产生自对准TiN阻挡层（24）。 可以在相同的退火过程中产生气隙（26）。 该方法可用于形成多层结构。
-
8.发明申请公开(公告)号：US20100187527A1
公开(公告)日：2010-07-29
申请号：US12671067
申请日：2008-07-29
IPC分类号： H01L23/52
CPC分类号： H01L23/576 , H01L24/73 , H01L2224/48091 , H01L2224/73265 , H01L2924/09701 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection layer (50, 50a, 50b) is arranged on a second side of the substrate (5) opposite to the first side. At least three through-substrate electrically-conductive connections (45) extend from the first side of the substrate (5) into the substrate (5) and in electrical contact with the electrically-conductive protection layer (50, 50a, 50b) on the second side of the substrate (5). A security circuit is arranged on the first side connected to the through-substrate electrically-conductive connections (45) and is arranged for measuring at least two resistance values (R12, R23, R34, R14, R13, R24) of the electrically-conductive protection layer (50, 50a, 50b) through the through-substrate electrically-conductive connections (45). The security circuit is further arranged for comparing the measured resistance values (R12, R23, R34, R14, R13, R24) with reference resistance values.
摘要翻译： 本发明涉及一种防篡改半导体器件，其包括基板（5），该基板包括布置在其第一侧上的电子电路。 导电保护层（50,50a，50b）布置在与第一侧相对的基板（5）的第二侧上。 至少三个贯穿基板的导电连接（45）从基板（5）的第一侧延伸到基板（5）中并与导电保护层（50,50a，50b）电接触 基板（5）的第二侧。 安全电路布置在与贯穿基板导电连接（45）连接的第一侧上，并且布置成用于测量导电的至少两个电阻值（R12，R23，R34，R14，R13，R24） 保护层（50,50a，50b）穿过贯通基板导电连接（45）。 安全电路还被布置为将测得的电阻值（R12，R23，R34，R14，R13，R24）与参考电阻值进行比较。
-
公开(公告)号：US20090302419A1
公开(公告)日：2009-12-10
申请号：US11720322
申请日：2005-11-25
IPC分类号： H01L27/06 , H01L21/02 , H01L21/302
CPC分类号： H01L28/84 , H01L27/1087 , H01L29/66181
摘要： In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench.
摘要翻译： 在该方法中，特别是非晶硅的第一层被沉积在具有沟槽的衬底的表面上。 该表面的一部分被保护层覆盖。 此后，第一层通过在衬底表面上进行干蚀刻处理而被除去，同时保持在沟槽内。
-
10.发明授权Method of manufacturing a semiconductor device comprising a capacitor with a ferroelectric dielectric, and semiconductor device comprising such a capacitor 失效制造包括具有铁电电介质的电容器的半导体器件的方法以及包括这种电容器的半导体器件
公开(公告)号：US5396095A
公开(公告)日：1995-03-07
申请号：US206916
申请日：1994-03-04
IPC分类号： H01G7/06 , H01L21/02 , H01L21/318 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/115 , H01L29/49 , H01L27/02
CPC分类号： H01L27/11502 , H01L28/55 , H01L29/49 , Y10S438/909
摘要： A semiconductor device in which a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in which a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.
摘要翻译： 一种半导体器件，其中在具有半导体元件（1）的半导体本体（3）的表面（10）上提供电容器（2），其中下电极（11），氧化铁电介质（12）和 上电极（13）依次设置，上电极不覆盖电介质的边缘，之后设置具有叠加金属导体轨迹的绝缘层（14）。 根据本发明，未被上电极（13）覆盖的电介质（12）的边缘涂覆有几乎不受氢气影响的涂层（14,20或30），之后将器件在氢气中加热 含气氛 在氢气气氛中加热中和在绝缘层上沉积导体轨迹期间产生的悬挂键，而涂层保护电介质免受氢的侵蚀。 因此，半导体器件具有较短的访问时间。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.015 秒)
