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    Conductors for microelectronic circuits and method of manufacture
    2.
    发明授权
    Conductors for microelectronic circuits and method of manufacture 失效
    微电子电路用导体及制造方法

    公开(公告)号：US6060388A

    公开(公告)日：2000-05-09

    申请号：US960208

    申请日：1997-10-29

    申请人： Hiroyuki Akatsu ,  Russell H. Arndt ,  Bradley P. Jones ,  George F. Ouimet

    发明人： Hiroyuki Akatsu ,  Russell H. Arndt ,  Bradley P. Jones ,  George F. Ouimet

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01P3/06 ,  H01L21/4763

    CPC分类号： H01L21/76877

    摘要： An integrated circuit (IC) conductor and the process of making the conductor. The conductor may be a monofilament conductor, a clad conductor or a coaxial conductor. A trench is formed in a dielectric layer. An outer material layer is deposited on the dielectric layer and in the trench, thick enough that the outer material layer merges together in a seam over the trench forming a void under the seam. The outer material layer is dielectric for the monofilament conductor, a cladding material for the clad conductor and conducting material for the coaxial conductor. The void is filled with a conductor for a monofilament or clad conductors. An inner dielectric liner layer is formed on the walls of the void and a core conductor is formed on the liner layer for the coaxial conductor.

    摘要翻译： 一种集成电路（IC）导体和制造导体的过程。 导体可以是单丝导体，包层导体或同轴导体。 在电介质层中形成沟槽。 外部材料层沉积在电介质层和沟槽中，其厚度足够使得外部材料层在沟槽上的接缝中合并在一起形成接缝下方的空隙。 外部材料层是用于单丝导体的电介质，用于包层导体的包覆材料和用于同轴导体的导电材料。 空隙填充有用于单丝或包层导体的导体。 内部电介质衬层形成在空隙的壁上，芯导体形成在用于同轴导体的衬垫层上。

    Bottle-shaped trench capacitor with enhanced capacitance
    5.
    发明授权
    Bottle-shaped trench capacitor with enhanced capacitance 有权
    具有增强电容的瓶形沟槽电容器

    公开(公告)号：US08021945B2

    公开(公告)日：2011-09-20

    申请号：US12423242

    申请日：2009-04-14

    申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

    摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

    摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

    BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE
    6.
    发明申请
    BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE 有权
    具有增强电容的瓶形TRENCH电容器

    公开(公告)号：US20100258904A1

    公开(公告)日：2010-10-14

    申请号：US12423242

    申请日：2009-04-14

    申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

    IPC分类号： H01L27/07 ,  H01L21/02

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

    摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

    摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

    TOOL FOR MANUFACTURING SEMICONDUCTOR STRUCTURES AND METHOD OF USE
    8.
    发明申请
    TOOL FOR MANUFACTURING SEMICONDUCTOR STRUCTURES AND METHOD OF USE 有权
    制造半导体结构的工具及其使用方法

    公开(公告)号：US20120326076A1

    公开(公告)日：2012-12-27

    申请号：US13169418

    申请日：2011-06-27

    申请人： Russell H. ARNDT ,  David F. Hilscher

    发明人： Russell H. ARNDT ,  David F. Hilscher

    IPC分类号： C09K13/08 ,  C23F1/08

    CPC分类号： C09K13/08 ,  H01L21/31111 ,  H01L21/67086

    摘要： A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NH4F to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.

    摘要翻译： 提供了一种工具和方法，用于混合多个部件并将多个部件的单一混合物馈送到工具中。 该方法包括调整蚀刻剂溶液的浓度。 该方法包括确定进入晶片处理工具的蚀刻室的多批晶片的每批晶片的蚀刻目标。 该方法还包括在单次运行期间将进入晶片处理工具的多批批晶片的每批晶片的40％NH 4 F浓度调节至49％HF。

    Tool for manufacturing semiconductor structures and method of use
    10.
    发明授权
    Tool for manufacturing semiconductor structures and method of use 有权
    制造半导体结构的工具及其使用方法

    公开(公告)号：US09005464B2

    公开(公告)日：2015-04-14

    申请号：US13169418

    申请日：2011-06-27

    申请人： Russell H. Arndt ,  David F. Hilscher

    发明人： Russell H. Arndt ,  David F. Hilscher

    IPC分类号： C03C15/00 ,  C03C25/68 ,  H01L21/302 ,  H01L21/461 ,  C09K13/08 ,  H01L21/311 ,  H01L21/67

    CPC分类号： C09K13/08 ,  H01L21/31111 ,  H01L21/67086

    摘要： A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NH4F to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.

    摘要翻译： 提供了一种工具和方法，用于混合多个部件并将多个部件的单一混合物馈送到工具中。 该方法包括调整蚀刻剂溶液的浓度。 该方法包括确定进入晶片处理工具的蚀刻室的多批晶片的每批晶片的蚀刻目标。 该方法还包括在单次运行期间将进入晶片处理工具的多批批晶片的每批晶片的40％NH 4 F浓度调节至49％HF。