公开(公告)号：US08489780B2

公开(公告)日：2013-07-16

申请号：US11644474

申请日：2006-12-21

申请人： Rajesh Sundaram ,  Rodney R. Rozman ,  Sanjay S. Talreja

发明人： Rajesh Sundaram ,  Rodney R. Rozman ,  Sanjay S. Talreja

IPC分类号： G06F3/00 ,  G06F1/32

CPC分类号： G11C16/30

摘要： Some embodiments of the invention may use a single control line signal as both a wake up signal and as an indicator of a device selection command. In a command-based protocol on a non-volatile memory bus, a host memory controller may assert a signal on a control line to bring all the memory devices on the bus into an operational mode, while concurrently placing a device selection command on the input/output lines. The memory device selected by the selection command may remain operational to perform a sequence of operations as directed by the host controller. The remaining (non-selected) memory devices may return to a sleep mode until a new signal on the control line is received, indicating a new selection command.

摘要翻译： 本发明的一些实施例可以使用单个控制线信号作为唤醒信号和作为设备选择命令的指示符。 在非易失性存储器总线上的基于命令的协议中，主机存储器控制器可以在控制线路上断言信号，以使总线上的所有存储器件进入操作模式，同时在输入端上设置设备选择命令 /输出线。 由选择命令选择的存储器件可以保持运行，以执行由主机控制器指导的操作序列。 剩余的（未选择的）存储器件可以返回睡眠模式，直到接收到控制线上的新信号，指示新的选择命令。

公开(公告)号：US5485422A

公开(公告)日：1996-01-16

申请号：US252684

申请日：1994-06-02

申请人： Mark E. Bauer ,  Kevin W. Frary ,  Sanjay S. Talreja

发明人： Mark E. Bauer ,  Kevin W. Frary ,  Sanjay S. Talreja

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5641

摘要： A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.

摘要翻译： 公开了一种存储器件，其包括具有m个可能状态的存储器单元，其中m至少为2.存储器件包括多路输出路径对，其中每个输出路径被耦合以感测存储器单元的状态，并且包括读取 路径电路，列负载电路和比较器。 在一对输出路径之间设置有用于响应于控制信号将比较器彼此耦合的开关电路。 对于单位读取操作，每个输出路径检测并输出相关存储单元的数据，并且控制信号无效。 当控制信号有效时，其中一个输出路径的读路径电路和列负载电路被禁止，并且开关电路将另一个读路径电路耦合到第二比较器，使得存储单元的状态由两个比较器 。

公开(公告)号：US5317535A

公开(公告)日：1994-05-31

申请号：US901110

申请日：1992-06-19

申请人： Sanjay S. Talreja ,  Duane Mills ,  Jahanshir J. Javanifard ,  Sachidanandan Sambandan

发明人： Sanjay S. Talreja ,  Duane Mills ,  Jahanshir J. Javanifard ,  Sachidanandan Sambandan

IPC分类号： G11C16/12 ,  G11C11/34 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C16/3427 ,  G11C16/12

摘要： In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.

摘要翻译： 在其中以行和列布置多个浮动栅场效应晶体管存储器件的快闪EEPROM存储器阵列中，其中利用字线来选择这些器件的行和位线来选择这些器件的列，其中组 这些设备被排列成可独立地可擦除的块，并且块被划分成用于存储待存储的字的较低字节和高字节的子块，当低位设置用于禁止字线到所有高字节子块的装置 要编程字节子块，当要编程高字节子块时禁止字线到所有低字节子块，用于在低字节子块时接地所有高字节子块的源 要编程高字节子块时，要对所有低字节子块的源进行接地编程。

公开(公告)号：US06920539B2

公开(公告)日：2005-07-19

申请号：US10183234

申请日：2002-06-26

申请人： Shekoufeh Qawami ,  Chaitanya S. Rajguru ,  Sanjay S. Talreja

发明人： Shekoufeh Qawami ,  Chaitanya S. Rajguru ,  Sanjay S. Talreja

IPC分类号： G06F13/16 ,  G06F12/00

CPC分类号： G06F13/161

摘要： Briefly, in accordance with an embodiment of the invention, a method and system to retrieve information from a memory is provided. The method may include transferring information from the memory in response to at least two synchronous burst read requests using pipelining.

摘要翻译： 简而言之，根据本发明的实施例，提供了一种从存储器检索信息的方法和系统。 该方法可以包括响应于使用流水线化的至少两个同步突发读取请求从存储器传送信息。

公开(公告)号：US06587373B2

公开(公告)日：2003-07-01

申请号：US10266779

申请日：2002-10-08

申请人： Sanjay S. Talreja

发明人： Sanjay S. Talreja

IPC分类号： G11C1604

CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C16/08

摘要： A multilevel cell memory may use an architecture in which bits from different words are stored in the same multilevel memory cell. This may improve access time because it is not necessary to sense both cells before the word can be outputted. Therefore, the access time may be improved by removing a serial element from the access chain.

公开(公告)号：US5742787A

公开(公告)日：1998-04-21

申请号：US419357

申请日：1995-04-10

申请人： Sanjay S. Talreja

发明人： Sanjay S. Talreja

IPC分类号： G11C16/10 ,  G06F12/00

CPC分类号： G11C16/10 ,  G11C16/102

摘要： A method of quickly aborting an automated program or erase sequence on a nonvolatile memory array in which each operation of the sequence is performed by a write state machine. During each operation of the program or erase sequence, the state of an abort signal is detected to determine whether or not the sequence should be aborted. If the abort signal is in a second state, the sequence continues to the next operation. If the abort signal is in a first state, the write state machine aborts the sequence and the nonvolatile memory array is placed in a read-only mode. The nonvolatile memory array is then available for user access.

摘要翻译： 一种在非易失性存储器阵列中快速地中止自动程序或擦除序列的方法，其中由写入状态机执行序列的每个操作。 在程序或擦除序列的每个操作期间，检测中止信号的状态以确定序列是否应该被中止。 如果中止信号处于第二状态，则该序列继续进行下一个操作。 如果中止信号处于第一状态，则写入状态机中止序列，并且将非易失性存储器阵列置于只读模式。 然后，非易失性存储器阵列可用于用户访问。

公开(公告)号：US5267196A

公开(公告)日：1993-11-30

申请号：US901279

申请日：1992-06-19

申请人： Sanjay S. Talreja ,  Peter K. Hazen ,  Sherif R. B. Sweha

发明人： Sanjay S. Talreja ,  Peter K. Hazen ,  Sherif R. B. Sweha

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/12 ,  G11C16/04 ,  G11C17/00

CPC分类号： G11C16/0416 ,  G11C5/025 ,  G11C5/063 ,  G11C8/12

摘要： A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell. The first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to a first data pin of the memory device such that the distances of the first and third memory cells of the first data bit group to a first sensing circuit are substantially minimized and are substantially equal. The second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to a second data pin of the memory device such that the distances of the second and fourth memory cells of the second data bit group to a second sensing circuit are substantially minimized and are substantially equal.

摘要翻译： 描述驻留在基板上的非易失性存储器件。 存储器件包括第一块和第二块。 第一块包括第一子块，其包括第一存储器单元，耦合到第一存储器单元的漏极的第一位线和耦合到第一存储器单元的源极的第一源极线。 第一块还包括第二子块，其包括第二存储器单元，耦合到第二存储单元的漏极的第二位线和耦合到第二存储器单元的源极的第二源极线。 第二块包括第三子块，其包括第三存储器单元，耦合到第三存储器单元的漏极的第三位线以及耦合到第三存储器单元的源极的第三源极线。 第二块还包括第四子块，其包括第四存储单元，耦合到第四存储单元的漏极的第四位线和耦合到第四存储单元的源极的第四源极线。 第一块的第一子块和第二块的第三子块在衬底上分组在一起以形成与存储器件的第一数据引脚相对应的第一数据位组，使得第一和第 第一数据位组的第三存储单元基本上最小化并且基本相等。 第一块的第二子块和第二块的第四子块在衬底上分组在一起以形成与存储器件的第二数据管脚相对应的第二数据位组，使得第二和 第二数据位组的第四存储单元基本上被最小化并且基本相等。

公开(公告)号：US06223290B1

公开(公告)日：2001-04-24

申请号：US09074475

申请日：1998-05-07

申请人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

IPC分类号： H04B116

CPC分类号： H04W12/12 ,  H04W88/02

摘要： A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

摘要翻译： 描述了一种用于控制电子系统的使用的方法和装置。 通过将至少一个唯一代码编程到电子系统的辅助存储器中来控制电子系统的使用。 辅助存储器是位于主存储器阵列空间外部的永久可锁存储器。 将唯一代码与至少一个组件代码进行比较。 基于唯一代码和组件代码之间的预定关系来控制电子系统的使用。

公开(公告)号：US6154819A

公开(公告)日：2000-11-28

申请号：US76298

申请日：1998-05-11

申请人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

IPC分类号： G06F12/14 ,  G11C16/22

CPC分类号： G11C16/22 ,  G06F12/1433

摘要： An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

摘要翻译： 公开了一种用于保护基于块的闪存可擦除可编程只读存储器（EPROM）装置中的存储块的装置。 非易失性存储器阵列包括能够被置于锁定状态或解锁状态的多个块。 易失性锁定寄存器和发送写保护信号和易失性锁存寄存器耦合到易失性存储器阵列中的可锁定块。 硬件覆盖线耦合到锁定寄存器和锁定寄存器。 当硬件覆盖线在第一逻辑状态下发送信号时，临时地覆盖锁定寄存器的操作。 锁定寄存器可用于防止相关锁定寄存器的编程。 锁定寄存器和锁定寄存器可以体现在静态存取存储器（SRAM）电路中。 命令缓冲器可以用于发送包括指定是否要改变锁定配置的第一命令和指定是否将块置于锁定状态，解锁状态或锁定状态的第二命令的两周期命令 。 锁定寄存器可能能够在设备通电期间被设置为仅锁定一次。

公开(公告)号：US5907700A

公开(公告)日：1999-05-25

申请号：US879084

申请日：1997-06-19

申请人： Sanjay S. Talreja ,  Rodney R. Rozman ,  Mickey Lee Fandrich ,  Bharat Pathak

发明人： Sanjay S. Talreja ,  Rodney R. Rozman ,  Mickey Lee Fandrich ,  Bharat Pathak

IPC分类号： G11C8/12 ,  G11C16/10 ,  G11C16/30 ,  G06F1/14 ,  G11C16/02

CPC分类号： G11C8/12 ,  G11C16/10 ,  G11C16/30

摘要： An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.

摘要翻译： 描述了操作控制方法和装置。 该装置包括定时器电路，闭锁电路和控制电路。 定时器电路在由起始信号启动的预定经过时间间隔的定时完成时提供完成信号。 如果完成信号在接收时未被阻塞，则阻塞电路接收完成信号并提供完成信号作为输出。 控制电路接收指示要执行操作的开始信号和指示是否存在将在一个步骤中阻止操作完成的条件的限制信号。 如果限制信号指示可以在单步中完成操作，则控制电路启动定时电路并控制单步骤的性能，直到接收完成信号。 如果限制信号表示在一个步骤中不能完成操作，则控制电路将单个步骤分成至少两个子步骤，在每个子步骤期间，控制电路启动定时电路并控制子步骤的性能， 一直到收到完成的信号。 控制电路在每个子步骤期间阻塞完成信号从阻塞电路的输出直到最后的子步骤。 对于一个实施例，要执行的操作是由写状态机指定的擦除操作，该擦除操作指定要在闪速存储器内擦除的擦除块。 或者，要执行的操作是由写状态机指定的程序操作，其指定要在闪速存储器内编程的数据。