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1.发明授权Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 失效在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量公开(公告)号：US07713829B2
公开(公告)日：2010-05-11
申请号：US11562735
申请日：2006-11-22
Applicant: Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
Inventor： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC: H01L21/8222 , H01L29/737
CPC classification number: H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
Abstract translation: 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。
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公开(公告)号：US20070161097A1
公开(公告)日：2007-07-12
申请号：US11517979
申请日：2006-09-08
Applicant: Phillip Green , Robert Johnson , Stuart Dunn
Inventor： Phillip Green , Robert Johnson , Stuart Dunn
Abstract: Mutant bacteria with improved poly-3-hydroxylalkanoate (PHA)-producing characteristics and methods of producing and using them are provided.
Abstract translation: 提供改良的聚-3-羟基烷酸（PHA）生产特性的突变细菌及其生产和使用方法。
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公开(公告)号：US06812545B2
公开(公告)日：2004-11-02
申请号：US10425270
申请日：2003-04-29
Applicant: James Stuart Dunn , David L. Harame , Jeffrey Bowman Johnson , Robb Allen Johnson , Louis DeWolf Lanzerotti , Stephen Arthur St. Onge
Inventor： James Stuart Dunn , David L. Harame , Jeffrey Bowman Johnson , Robb Allen Johnson , Louis DeWolf Lanzerotti , Stephen Arthur St. Onge
IPC: H01L27082
CPC classification number: H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.
Abstract translation: 一种外延基极双极晶体管，包括在单晶单个衬底上的外延单晶层; 半导体表面上的凸起的发射极; 在半导体衬底的表面上凸起的非本征基底; 凸起的发射极和凸出的外部基极之间的绝缘体，其中所述绝缘体是间隔物; 以及来自凸起的发射极和凸出的外部基极的扩散，以在所述单晶衬底中提供发射极扩散和非本征基极扩散，其中所述发射极扩散具有发射极扩散结深度，并且其中所述发射极延伸到所述衬底表面， 所述基底延伸到所述衬底表面，其中所述发射极与基底表面的高度差小于所述发射极结深度的20％以及其制造方法。
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4.发明授权公开(公告)号：US06597050B1
公开(公告)日：2003-07-22
申请号：US09574810
申请日：2000-05-19
Applicant: James Stuart Dunn , Peter Brian Gray , Kenneth Knetch Kieft, III , Nicholas Theodore Schmidt , Stephen St. onge
Inventor： James Stuart Dunn , Peter Brian Gray , Kenneth Knetch Kieft, III , Nicholas Theodore Schmidt , Stephen St. onge
IPC: H01L3100
CPC classification number: H01L29/872
Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.
Abstract translation: 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全接合的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。
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公开(公告)号：US06426265B1
公开(公告)日：2002-07-30
申请号：US09774126
申请日：2001-01-30
Applicant: Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
Inventor： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC: H01L21331
CPC classification number: H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
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Patent Agency Ranking
公开(公告)号：US6121122A
公开(公告)日：2000-09-19
申请号：US312945
申请日：1999-05-17
Applicant: James Stuart Dunn , Peter Brian Gray , Kenneth Knetch Kieft, III , Nicholas Theodore Schmidt , Stephen St. onge
Inventor： James Stuart Dunn , Peter Brian Gray , Kenneth Knetch Kieft, III , Nicholas Theodore Schmidt , Stephen St. onge
IPC: H01L29/872 , H01L29/64 , H01L29/56 , H01L29/62
CPC classification number: H01L29/872
Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.
Abstract translation: 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全界定的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。
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公开(公告)号：US20130259884A1
公开(公告)日：2013-10-03
申请号：US13825801
申请日：2011-09-23
Applicant: Nigel Stuart Dunn-Coleman , Maria R. Diaz-Torres , Brian Miller
Inventor： Nigel Stuart Dunn-Coleman , Maria R. Diaz-Torres , Brian Miller
CPC classification number: C07K7/08 , A61K39/0002 , A61K39/35 , C07K7/06 , C07K14/37 , C07K14/415 , C07K14/435
Abstract: The application discloses peptides capable of preventing or treating fungal disease, including fungal allergy disease.
Abstract translation: 本申请公开了能够预防或治疗真菌性疾病（包括真菌性过敏性疾病）的肽。
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8.发明授权Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme 失效使用奇数积分方案制造堆叠多晶硅和MOS电容器的方法公开(公告)号：US06833299B2
公开(公告)日：2004-12-21
申请号：US10292204
申请日：2002-11-12
Applicant: Douglas D. Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
Inventor： Douglas D. Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
IPC: H01L218244
Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
Abstract translation: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。
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9.发明授权Poly-poly/MOS capacitor having a gate encapsulating first electrode layer 有权具有封装了第一电极层的栅极的多晶硅/ MOS电容器公开(公告)号：US06507063B2
公开(公告)日：2003-01-14
申请号：US09551168
申请日：2000-04-17
Applicant: Douglas D. Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
Inventor： Douglas D. Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
IPC: H01L27108
Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.
Abstract translation: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。
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10.发明授权Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme 有权使用SiGe BiCMOS集成方案制造多晶硅电容器的方法公开(公告)号：US06440811B1
公开(公告)日：2002-08-27
申请号：US09745361
申请日：2000-12-21
Applicant: Douglas Duane Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
Inventor： Douglas Duane Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
IPC: H01L218228
CPC classification number: H01L28/40 , H01L27/0635
Abstract: A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.
Abstract translation: 一种用于制造与BiCMOS工艺集成的多晶硅电容器的方法，包括在沉积CMOS晶体管的栅电极期间形成多晶硅电容器的下板电极; 以及在异质结双极晶体管的SiGe基区的生长期间形成上SiGe板电极。
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