公开(公告)号：US20130334290A1

公开(公告)日：2013-12-19

申请号：US13592051

申请日：2012-08-22

申请人： Young Ju LEE ,  Yun Bog KIM ,  Seon Young MYOUNG ,  Suk Jin HAM ,  Seong Chan PARK ,  Hyun Jung LEE

发明人： Young Ju LEE ,  Yun Bog KIM ,  Seon Young MYOUNG ,  Suk Jin HAM ,  Seong Chan PARK ,  Hyun Jung LEE

IPC分类号： B23K3/053 ,  B23K1/00

CPC分类号： B23K3/0623

摘要： Disclosed herein is a solder paste droplet ejection apparatus including: a nozzle cap forming an appearance and including a heating electric wire provided inside thereof; a nozzle unit formed inside the nozzle cap, spaced apart from the nozzle cap, and surrounded by the nozzle cap; an ejection probe formed inside the nozzle unit, spaced apart from the nozzle unit, and surrounded by the nozzle unit; and a transfer unit formed in a top portion of the nozzle cap and used for a minute movement, wherein a solder paste supplied in a space between the nozzle unit and the ejection probe is ejected in a droplet shape along the ejection probe.

摘要翻译： 这里公开了一种焊锡膏液滴喷射装置，其包括形成外观的喷嘴帽，并且包括设置在其内部的加热电线; 喷嘴单元，其形成在所述喷嘴盖的内部，与所述喷嘴帽间隔开并且被所述喷嘴盖包围; 形成在喷嘴单元内的喷嘴，与喷嘴单元间隔开并被喷嘴单元包围; 以及形成在所述喷嘴帽的顶部并用于微小移动的转印单元，其中在所述喷嘴单元和所述喷射探针之间的空间中供应的焊膏沿着所述喷射探针以液滴形式喷射。

公开(公告)号：US20130292457A1

公开(公告)日：2013-11-07

申请号：US13554006

申请日：2012-07-20

申请人： Hyun Jung Lee ,  Young Ju Lee ,  Yun Bog Kim ,  Seon Young Myoung ,  Suk Jin Ham ,  Seong Chan Park

发明人： Hyun Jung Lee ,  Young Ju Lee ,  Yun Bog Kim ,  Seon Young Myoung ,  Suk Jin Ham ,  Seong Chan Park

IPC分类号： B23K35/02 ,  B23K1/00

CPC分类号： B23K35/0244 ,  B23K3/0623 ,  B23K3/08 ,  B23K3/087 ,  B23K35/0222 ,  B23K35/0227 ,  Y10T428/24174

摘要： Disclosed herein are a solder sheet and a soldering method using the same. The solder sheet includes: a plurality of solder rods arranged to have a uniform height h and an area density N; and a support having an adhesive formed on one surface thereof and supporting the plurality of solder rods such that one end of each of the plurality of solder rods is attached to be perpendicular to the surface on which the adhesive is formed. Solder bumps can be formed on soldering portions of the substrate by using the solder sheet through a single process without a mask, and thus, the process can be simplified, costs can be reduced, and a defect rate can be lowered, thereby enhancing reliability.

摘要翻译： 这里公开了一种焊料片和使用其的焊接方法。 焊料片包括：多个焊料棒，其布置成具有均匀的高度h和面积密度N; 以及具有在其一个表面上形成的粘合剂并且支撑多个焊料棒的支撑件，使得多个焊料棒中的每一个的一端附接成垂直于其上形成有粘合剂的表面。 可以通过在没有掩模的情况下通过单个工艺使用焊料片而在基板的焊接部分上形成焊料凸块，因此可以简化工艺，可以降低成本，并且可以降低缺陷率，从而提高可靠性。

公开(公告)号：US20130038982A1

公开(公告)日：2013-02-14

申请号：US13413574

申请日：2012-03-06

申请人： Kwang Jik Lee ,  Suk Jin Ham ,  Ji Hyuk Lim

发明人： Kwang Jik Lee ,  Suk Jin Ham ,  Ji Hyuk Lim

IPC分类号： H01G4/005 ,  B05D1/18 ,  B05D3/12 ,  B05D5/12

CPC分类号： H01G4/008 ,  H01G4/005

摘要： Disclosed herein are a multilayer ceramic condenser and a method for manufacturing the same. The multilayer ceramic condenser includes inner metal electrode layers formed within a magnetic layer, and conductive layers each formed between the inner metal electrode layers, and a method for manufacturing the same.According to the present invention, a contact between the inner metal electrode layers in the multilayer ceramic condenser can be prevented, thereby reducing the manufacturing loss due to occurrence of short circuits and improving thermal stability, by forming an ultrathin conducting layer with a thickness of about 10 nm or less between the inner metal electrode layers. Therefore, the multilayer ceramic condenser can be ensured to have excellent reliability to meet the demands of markets requesting a high-capacity multilayer ceramic condenser (MLCC) having high performance, small size, and light weight.

摘要翻译： 本文公开了一种多层陶瓷冷凝器及其制造方法。 多层陶瓷电容器包括形成在磁性层内的内部金属电极层和各自形成在内部金属电极层之间的导电层及其制造方法。 根据本发明，可以防止多层陶瓷电容器中的内部金属电极层之间的接触，从而通过形成厚度约为的厚度的超薄导电层来减少由于短路的发生而产生的制造损失并提高热稳定性 内侧金属电极层之间为10nm以下。 因此，可以确保多层陶瓷冷凝器具有优异的可靠性，以满足市场要求具有高性能，小尺寸和重量轻的高容量多层陶瓷电容器（MLCC）的需求。

公开(公告)号：US20120276372A1

公开(公告)日：2012-11-01

申请号：US13293992

申请日：2011-11-10

申请人： Kwang Jik LEE ,  Suk Jin Ham ,  Ji Hyuk Lim

发明人： Kwang Jik LEE ,  Suk Jin Ham ,  Ji Hyuk Lim

IPC分类号： B32B3/00 ,  H05K3/10 ,  B32B15/04

CPC分类号： H01G4/306 ,  B23B3/00 ,  H01G4/008 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/1209 ,  H01G4/30 ,  Y10T29/49155 ,  Y10T428/265 ,  Y10T428/31678

摘要： There are provided a multilayer thin film for a ceramic electronic component and a method of manufacturing the same. The multilayer thin film includes a substrate; and a ceramic layer and a metal layer alternately formed on at least one of upper and lower surfaces of the substrate, wherein at least one of the ceramic layer and the metal layer has a height corresponding to a thickness of at least one of a plurality of particles arranged on a plane. With the multilayer thin film for a ceramic electronic component, the number of layers increases and a distance between electrodes decreases, whereby capacitance may increase.

摘要翻译： 提供了一种用于陶瓷电子部件的多层薄膜及其制造方法。 多层薄膜包括基板; 以及交替地形成在所述基板的上表面和下表面中的至少一个上的陶瓷层和金属层，其中所述陶瓷层和所述金属层中的至少一个具有对应于多个 颗粒排列在平面上。 利用陶瓷电子部件的多层薄膜，层数增加，电极间距离减小，电容量增大。

公开(公告)号：US07906841B2

公开(公告)日：2011-03-15

申请号：US11447971

申请日：2006-06-07

申请人： Byung-gil Jeong ,  In-sang Song ,  Woon-bae Kim ,  Min-seog Choi ,  Suk-jin Ham ,  Ji-hyuk Lim

发明人： Byung-gil Jeong ,  In-sang Song ,  Woon-bae Kim ,  Min-seog Choi ,  Suk-jin Ham ,  Ji-hyuk Lim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L21/00

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2924/01079 ,  H01L2924/16235

摘要： A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.

摘要翻译： 晶圆级封装芯片和封装芯片制造方法。 封装芯片包括器件衬底，安装在器件衬底上的电路模块，沉积在器件衬底的预定区域上的结合层，在电路模块上形成空腔的保护帽，并通过结合层结合到器件衬底 以及形成在接合层和保护盖的预定区域上的封装部。 因此，本发明可以最大限度地减少芯片处理时对芯片的损害，并防止水分引入芯片内部。

公开(公告)号：US07755151B2

公开(公告)日：2010-07-13

申请号：US11415099

申请日：2006-05-02

申请人： Ji-hyuk Lim ,  Jun-sik Hwang ,  Woon-bae Kim ,  Suk-jin Ham ,  Jong-oh Kwon ,  Moon-chul Lee ,  Chang-youl Moon

发明人： Ji-hyuk Lim ,  Jun-sik Hwang ,  Woon-bae Kim ,  Suk-jin Ham ,  Jong-oh Kwon ,  Moon-chul Lee ,  Chang-youl Moon

IPC分类号： H01L29/82 ,  H01L23/04 ,  H01L21/00

CPC分类号： H03H9/1092

摘要： A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.

摘要翻译： 用于声表面波器件的晶片级封装及其制造方法包括在器件晶片的上表面上形成有SAW元件的SAW器件; 接合在所述SAW元件的上部的盖晶片; 在所述盖晶片和所述SAW器件之间容纳所述SAW元件的空腔部; 帽盖，形成在盖晶片的上表面上; 以及金属线，其形成为穿透盖晶片以电连接帽垫和SAW元件，器件晶片和盖晶片由相同的材料制成。

公开(公告)号：US07408257B2

公开(公告)日：2008-08-05

申请号：US11390220

申请日：2006-03-28

申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

IPC分类号： H01L23/04

CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

公开(公告)号：US07285865B2

公开(公告)日：2007-10-23

申请号：US11396544

申请日：2006-04-04

申请人： Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song ,  Ji-hyuk Lim ,  Suk-jin Ham ,  Byung-gil Jeong

发明人： Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song ,  Ji-hyuk Lim ,  Suk-jin Ham ,  Byung-gil Jeong

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/053 ,  B81C1/00269 ,  H01L23/055 ,  H01L23/10 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/564 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/11831 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/274 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48463 ,  H01L2224/83851 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2224/29075 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.

公开(公告)号：US20070020817A1

公开(公告)日：2007-01-25

申请号：US11447971

申请日：2006-06-07

申请人： Byung-gil Jeong ,  In-sang Song ,  Woon-bae Kim ,  Min-seog Choi ,  Suk-jin Ham ,  Ji-hyuk Lim

发明人： Byung-gil Jeong ,  In-sang Song ,  Woon-bae Kim ,  Min-seog Choi ,  Suk-jin Ham ,  Ji-hyuk Lim

IPC分类号： H01L21/00

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2924/01079 ,  H01L2924/16235

摘要： A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.

摘要翻译： 晶圆级封装芯片和封装芯片制造方法。 封装芯片包括器件衬底，安装在器件衬底上的电路模块，沉积在器件衬底的预定区域上的结合层，在电路模块上形成空腔的保护帽，并通过结合层结合到器件衬底 以及形成在接合层和保护盖的预定区域上的封装部。 因此，本发明可以最大限度地减少在芯片处理时对芯片的损害，并防止水分引入芯片内部。

公开(公告)号：US20070012655A1

公开(公告)日：2007-01-18

申请号：US11396544

申请日：2006-04-04

申请人： Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song ,  Ji-hyuk Lim ,  Suk-jin Ham ,  Byung-gil Jeong

发明人： Jong-oh Kwon ,  Woon-bae Kim ,  In-sang Song ,  Ji-hyuk Lim ,  Suk-jin Ham ,  Byung-gil Jeong

IPC分类号： H01B13/00 ,  H01L21/30 ,  H01L21/00 ,  H01L23/52

CPC分类号： H01L23/053 ,  B81C1/00269 ,  H01L23/055 ,  H01L23/10 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/564 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/11831 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/274 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48463 ,  H01L2224/83851 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2224/29075 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.

摘要翻译： 提供微型封装，多堆叠微型封装及其制造方法。 根据本发明的微型封装包括用于安装器件的器件基板，作为电路模块; 保护装置的保护帽; 通过在器件基板上的预定区域上图案化而形成的结合物质将器件基板和保护盖接合; 形成在器件基板的一部分上的层和粘合物质的保护盖的一部分和外侧; 通过蚀刻掉保护盖的另一部分并且通过接合物质电连接到器件基板的上表面而形成的通孔; 在通孔上形成的阻挡金属（UBM）; 以及形成在UBM上的作为外部信号的连接端子的焊料保险杠。 如上所述，本发明具有保证气密密封的优点，因为上述层防止从外部吸湿，同时降低了对包装内部装置的损坏的可能性，因为处理温度在晶片接合后下降到150°以下 涉及使用聚合物物质作为结合物质。