公开(公告)号：US08587114B2

公开(公告)日：2013-11-19

申请号：US12897933

申请日：2010-10-05

Applicant: Suresh D. Kadakia ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jeffrey A. Zitz

Inventor： Suresh D. Kadakia ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jeffrey A. Zitz

IPC: H01L23/12

CPC classification number: H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/433 ,  H01L23/4338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

公开(公告)号：US07472836B2

公开(公告)日：2009-01-06

申请号：US11768312

申请日：2007-06-26

Applicant: Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

Inventor： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC: G06K19/05

CPC classification number: G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract translation: 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US06179951B2

公开(公告)日：2001-01-30

申请号：US09263965

申请日：1999-03-05

Applicant: Govindarajan Natarajan ,  John U. Knickerbocker ,  Suresh D. Kadakia ,  Abubaker S. Shagan

Inventor： Govindarajan Natarajan ,  John U. Knickerbocker ,  Suresh D. Kadakia ,  Abubaker S. Shagan

IPC: B32B3120

CPC classification number: B32B37/0023 ,  B32B37/26 ,  B32B2315/02 ,  H01L21/4857

Abstract: The present invention relates generally to a new apparatus and method for forming non-planar surfaces in substrates. More particularly, the invention encompasses an apparatus and a method for fabricating non-planar surfaces in semiconductor substrates wherein at least one zero compression set pad, such as a closed cell porous pad in combination with at least one elastic pad is placed over the non-planar surface prior to lamination and is caused to conform to the contour of the non-planar surface, thus preventing collapse of, or damage to, the non-planar features, such as, shelves or corners during the lamination process. After the lamination process, the zero compression set pad are conveniently removed from the non-planar surface area without causing any damage to the non-planar surface features, such as, shelves or corners or having any paste pull-outs. These zero compression set pads can be reused multiple number of times to form these MLC cavity substrates or similar other structures or features.

Abstract translation: 本发明一般涉及用于在基片中形成非平面表面的新装置和方法。 更具体地说，本发明包括一种用于在半导体衬底中制造非平面表面的装置和方法，其中至少一个零压缩固定衬垫，例如与至少一个弹性衬垫组合的闭孔多孔垫， 平坦表面，并且使其符合非平面表面的轮廓，从而防止在层压过程期间非平面特征（例如，搁板或角部）的塌陷或损坏。 在层压过程之后，零压缩固定垫可以方便地从非平面表面区域移除，而不会对非平面表面特征（例如，搁板或角落）或具有任何糊状物拉出造成任何损坏。 这些零压缩设定焊盘可以重复使用多次以形成这些MLC腔体衬底或类似的其他结构或特征。

公开(公告)号：US5243140A

公开(公告)日：1993-09-07

申请号：US771707

申请日：1991-10-04

Applicant: Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

Inventor： Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/5382 ,  H01L21/485 ,  H01L2224/16225 ,  H01L2924/19107

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：US20120196408A1

公开(公告)日：2012-08-02

申请号：US13433468

申请日：2012-03-29

Applicant: Suresh D. KADAKIA ,  Kamal K. SIKKA ,  Hilton T. TOY ,  Jeffrey A. ZITZ

Inventor： Suresh D. KADAKIA ,  Kamal K. SIKKA ,  Hilton T. TOY ,  Jeffrey A. ZITZ

IPC: H01L21/56

CPC classification number: H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/433 ,  H01L23/4338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

Abstract translation: 提供了一种多芯片电子封装及其制造方法。 多芯片封装包括安装在芯片载体上的多个芯片。 多芯片封装还包括使用接合材料或压缩密封件安装在芯片载体上的盖和从盖延伸的至少一个单个活塞。 每个活塞覆盖多个芯片的整个多个芯片。

公开(公告)号：US07281667B2

公开(公告)日：2007-10-16

申请号：US10907761

申请日：2005-04-14

Applicant: Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

Inventor： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC: G06K19/06

CPC classification number: G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract translation: 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US5831810A

公开(公告)日：1998-11-03

申请号：US701029

申请日：1996-08-21

Applicant: Kenneth A. Bird ,  Peter J. Brofman ,  Francis F. Cappo, Jr. ,  Jason L. Frankel ,  Suresh D. Kadakia ,  Sarah Huffsmith Knickerbocker ,  Scott A. Sikorski

Inventor： Kenneth A. Bird ,  Peter J. Brofman ,  Francis F. Cappo, Jr. ,  Jason L. Frankel ,  Suresh D. Kadakia ,  Sarah Huffsmith Knickerbocker ,  Scott A. Sikorski

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/64 ,  H01G4/00

CPC classification number: H01L24/49 ,  H01L23/13 ,  H01L23/642 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30105

Abstract: An electronic component package comprising a substrate having at least one die-receiving cavity formed therein, the cavity being defined by a die-receiving surface and an inner sidewall having a terraced contour, the substrate having an exterior surface bordering the cavity perimeter, the inner sidewall extending between the die-receiving surface and the substrate exterior surface, and at least one capacitor positioned completely within the cavity and mounted to the terraced contour of the inner sidewall.

Abstract translation: 一种电子部件封装，包括：衬底，其具有形成在其中的至少一个管芯接收腔，所述空腔由管芯接收表面和具有梯形轮廓的内侧壁限定，所述衬底具有与所述腔周界接壤的外表面， 在模具接收表面和基板外表面之间延伸的侧壁以及至少一个完全位于腔体内并且安装到内侧壁的梯形轮廓的电容器。

公开(公告)号：US08445331B2

公开(公告)日：2013-05-21

申请号：US13433468

申请日：2012-03-29

Applicant: Suresh D. Kadakia ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jeffrey A. Zitz

Inventor： Suresh D. Kadakia ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jeffrey A. Zitz

IPC: H01L21/44

CPC classification number: H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/433 ,  H01L23/4338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

公开(公告)号：US20090145973A1

公开(公告)日：2009-06-11

申请号：US12348364

申请日：2009-01-05

Applicant: Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

Inventor： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC: G06K19/06

CPC classification number: G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract translation: 防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

公开(公告)号：US07806341B2

公开(公告)日：2010-10-05

申请号：US12348364

申请日：2009-01-05

Applicant: Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

Inventor： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC: G06K19/05

CPC classification number: G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract translation: 防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。