公开(公告)号：US20140144864A1

公开(公告)日：2014-05-29

申请号：US14122080

申请日：2011-11-15

Applicant: Su-Jae LEE ,  Seong-Jae LEE ,  Tae-Keun LEE ,  Sun-Hee LEE

Inventor： Seong-Jae Lee

IPC: B65D41/02

CPC classification number: B65D41/02 ,  B65D51/28 ,  B65D51/2835 ,  B65D51/2864 ,  B65D2251/08

Abstract: A reception apparatus to be coupled to container necks having different sizes has a main body in which a reception unit comprising a storage space is formed, and a lower side having a threaded part. Threads fitted to the sizes of the container necks are formed within the thread portion of the reception apparatus. The threads are formed to be capable of being coupled to a plurality of container necks, or formed of elastic threads integrally or separately produced.

Abstract translation: 要连接到具有不同尺寸的容器颈部的接收装置具有形成包括存储空间的接收单元和具有螺纹部分的下侧的主体。 在接收装置的螺纹部分内形成有适合容器颈部尺寸的螺纹。 螺纹形成为能够联接到多个容器颈部，或者由整体地或单独地制造的弹性线形成。

公开(公告)号：US08633056B2

公开(公告)日：2014-01-21

申请号：US12723596

申请日：2010-03-12

Applicant: Hyung Jun Jeon ,  Tae Keun Lee ,  Sung Soo Kim

Inventor： Hyung Jun Jeon ,  Tae Keun Lee ,  Sung Soo Kim

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.

Abstract translation: 一种制造集成电路封装系统的方法包括：在其上形成具有器件的衬底，形成具有平面顶表面的封装，以覆盖器件和跨越封装的提取侧的衬底，以及在封装中形成凹部 从平面顶面。

公开(公告)号：US08114771B2

公开(公告)日：2012-02-14

申请号：US11615923

申请日：2006-12-22

Applicant: Hyung Jun Jeon ,  Tae Keun Lee ,  Young Chan Ko

Inventor： Hyung Jun Jeon ,  Tae Keun Lee ,  Young Chan Ko

IPC: H01L21/44

CPC classification number: H01L24/72 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.

Abstract translation: 提供了一种半导体晶片级封装系统，包括提供具有通孔通孔的半导体衬底和导电涂层，通过用导电材料填充通孔通孔来形成填充通孔，将封装衬底耦合到填充通孔，以及 从半导体衬底和封装衬底分离芯片级封装。

公开(公告)号：US08030755B2

公开(公告)日：2011-10-04

申请号：US11307532

申请日：2006-02-10

Applicant: Sangkwon Lee ,  Tae Keun Lee

Inventor： Sangkwon Lee ,  Tae Keun Lee

IPC: H01L23/10

CPC classification number: H01L23/4334 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system is provided forming a substrate having an integrated circuit die thereon, thermally connecting a heat slug and a resilient thermal structure to the integrated circuit die, and encapsulating the resilient thermal structure.

Abstract translation: 提供一种集成电路封装系统，其形成具有集成电路管芯的基板，将散热块和弹性热结构热连接到集成电路管芯，并封装弹性热结构。

公开(公告)号：US20080029911A1

公开(公告)日：2008-02-07

申请号：US11462303

申请日：2006-08-03

Applicant: Hyung Jun Jeon ,  Tae Keun Lee ,  Sung Soo Kim

Inventor： Hyung Jun Jeon ,  Tae Keun Lee ,  Sung Soo Kim

IPC: H01L23/28 ,  H01L21/00

CPC classification number: H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system is provided including forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.

Abstract translation: 提供了一种集成电路封装系统，包括在其上形成具有器件的衬底，形成具有平坦顶表面的封装以覆盖器件，衬底跨越封装的提取侧，以及在封装中从平面形成凹部 顶面。

公开(公告)号：US07309622B2

公开(公告)日：2007-12-18

申请号：US11307350

申请日：2006-02-01

Applicant: Minseok Kim ,  Tae Keun Lee

Inventor： Minseok Kim ,  Tae Keun Lee

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes providing a substrate. An integrated circuit is attached to the substrate. A plurality of support bars is formed on the substrate. A plurality of adhesive structures is formed. A heat sink is attached to the plurality of adhesive structures. The integrated circuit is encapsulated. The support bars are removed.

Abstract translation: 集成电路封装系统包括提供衬底。 集成电路连接到基板。 在基板上形成多个支撑杆。 形成多个粘合剂结构。 散热器附接到多个粘合剂结构。 集成电路封装。 支撑杆被移除。

公开(公告)号：US08853686B2

公开(公告)日：2014-10-07

申请号：US13587611

申请日：2012-08-16

Applicant: Ji Eun Chae ,  Jung Eun Ahn ,  Tae Keun Lee

Inventor： Ji Eun Chae ,  Jung Eun Ahn ,  Tae Keun Lee

IPC: H01L21/44 ,  H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1225 ,  H01L27/1288 ,  H01L27/3276 ,  H01L2227/323

Abstract: A flat panel display device with an oxide thin film transistor and a fabricating method thereof are disclosed. The fabricating method of the flat panel display device includes: preparing a substrate defined into a pixel region and a pad contact region; forming a gate electrode and a link line; forming a pixel electrode within the pixel region; forming an oxide layer on the substrate provided with the pixel electrode; forming a passivation layer on the substrate and performing a formation process of contact holes to expose the link line; and forming a second transparent conductive material film on the substrate.

Abstract translation: 公开了一种具有氧化物薄膜晶体管的平板显示装置及其制造方法。 平板显示装置的制造方法包括：准备限定为像素区域和衬垫接触区域的衬底; 形成栅电极和连接线; 在所述像素区域内形成像素电极; 在设置有像素电极的基板上形成氧化物层; 在所述基板上形成钝化层，并进行接触孔的形成处理以暴露所述连接线; 以及在所述基板上形成第二透明导电材料膜。

公开(公告)号：US20130032954A1

公开(公告)日：2013-02-07

申请号：US13649834

申请日：2012-10-11

Applicant: Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。

公开(公告)号：US08304922B2

公开(公告)日：2012-11-06

申请号：US12729204

申请日：2010-03-22

Applicant: Sangkwon Lee ,  Tae Keun Lee

Inventor： Sangkwon Lee ,  Tae Keun Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC classification number: H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48475 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83801 ,  H01L2224/85051 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.

Abstract translation: 半导体封装系统包括提供具有延伸穿过衬底的多个热通孔的衬底。 焊接掩模位于多个热通孔上。 使用焊接掩模在多个热通孔中的至少一些上形成多个导热凸块。 集成电路芯片附接到多个导热凸块。 密封剂封装集成电路管芯。

公开(公告)号：US08304874B2

公开(公告)日：2012-11-06

申请号：US11608826

申请日：2006-12-09

Applicant: Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。