公开(公告)号：US08164160B2

公开(公告)日：2012-04-24

申请号：US12155232

申请日：2008-05-30

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L29/92

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0805 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

摘要翻译： 根据本发明的半导体器件具有多层布线结构，其层叠并设置多个夹着绝缘膜的多层布线结构，并且包括：以铜为主要成分的铜线; 形成在铜线上的绝缘膜; 铝线，其以铝为主要成分，并形成在所述绝缘膜上，以通过形成为穿透所述绝缘膜的通孔与所述铜线电连接; 和形成在铝线上的表面保护膜; 并且所述表面保护膜形成有用于使铝线的一部分暴露于与外部部分电连接的电极焊盘的焊盘开口。

公开(公告)号：US20100190335A1

公开(公告)日：2010-07-29

申请号：US12659602

申请日：2010-03-15

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed metallic element. After this coating with the alloy film, a copper film is laminated on the insulating film to fill up the wiring trench. Then, unnecessary portions of the copper film outside the wiring trench are removed, so that the surface of the copper film remaining in the wiring trench is generally flush with the surface of the insulating film. Thereafter heat treatment is performed. The prescribed metallic element is deposited on the wiring trench due to this heat treatment. Then, the prescribed metallic element deposited on the wiring trench is removed.

摘要翻译： 在制造本发明的半导体器件的方法中，在绝缘膜的表面上形成布线沟槽，然后用由含铜的合金材料制成的合金膜涂覆该布线沟槽的内表面， 规定的金属元素。 在用合金膜涂覆之后，在绝缘膜上层压铜膜以填充布线沟槽。 然后，除去布线沟槽外部的铜膜的不必要部分，使得残留在布线沟槽中的铜膜的表面与绝缘膜的表面大致齐平。 然后进行热处理。 由于这种热处理，规定的金属元素沉积在布线沟槽上。 然后，去除沉积在布线沟槽上的规定金属元素。

公开(公告)号：US20080296772A1

公开(公告)日：2008-12-04

申请号：US12155231

申请日：2008-05-30

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L23/48

CPC分类号： H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L28/60 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005 ,  H01L2924/01004

摘要： A semiconductor device according to the present invention includes: a lower wire having copper as a main component; an insulating film formed on the lower wire; an upper wire formed on the insulating film; a tungsten plug penetrating through the insulating film and formed of tungsten for electrically connecting the lower wire and the upper wire; and a barrier layer interposed between the lower wire and the tungsten plug; and the barrier layer including a tantalum film contacting the lower wire and a titanium nitride film contacting the tungsten plug.

摘要翻译： 根据本发明的半导体器件包括：以铜为主要成分的下线; 形成在下线上的绝缘膜; 形成在绝缘膜上的上部线; 穿过绝缘膜并由钨形成的用于电连接下线和上线的钨塞; 以及插入在所述下线和所述钨插塞之间的阻挡层; 并且阻挡层包括接触下线的钽膜和与钨插塞接触的氮化钛膜。

公开(公告)号：US08125084B2

公开(公告)日：2012-02-28

申请号：US12445168

申请日：2007-10-11

申请人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

发明人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/2855 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion of the barrier layer defined between the boundary portions.

摘要翻译： 根据本发明的半导体器件包括：半导体衬底; 设置在半导体衬底上的第一铜互连; 绝缘层，设置在所述第一铜互连上并且具有穿过其延伸到所述第一铜互连的孔; 由含钽材料构成并且覆盖所述孔的至少一个侧壁和暴露在所述孔中的所述第一铜互连的一部分的阻挡层; 以及第二铜互连，其与阻挡层紧密接触并且经由阻挡层电连接到第一铜互连; 其中所述阻挡层具有氮浓度分布，使得所述材料中包含的氮的浓度在与所述第一铜互连相邻的所述阻挡层的边界部分中以及在与所述第二铜互连相邻的所述势垒层的边界部分中变低 铜互连并且在边界部分之间限定的阻挡层的中间部分中较高。

公开(公告)号：US20100032837A1

公开(公告)日：2010-02-11

申请号：US12445168

申请日：2007-10-11

申请人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

发明人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/2855 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion of the barrier layer defined between the boundary portions.

摘要翻译： 根据本发明的半导体器件包括：半导体衬底; 设置在半导体衬底上的第一铜互连; 绝缘层，设置在所述第一铜互连上并且具有穿过其延伸到所述第一铜互连的孔; 由含钽材料构成并且覆盖所述孔的至少一个侧壁和暴露在所述孔中的所述第一铜互连的一部分的阻挡层; 以及第二铜互连，其与阻挡层紧密接触并且经由阻挡层电连接到第一铜互连; 其中所述阻挡层具有氮浓度分布，使得所述材料中包含的氮的浓度在与所述第一铜互连相邻的所述阻挡层的边界部分中以及在与所述第二铜互连相邻的所述势垒层的边界部分中变低 铜互连并且在边界部分之间限定的阻挡层的中间部分中较高。

公开(公告)号：US20080296730A1

公开(公告)日：2008-12-04

申请号：US12155232

申请日：2008-05-30

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L29/92 ,  H01L23/52

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0805 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

摘要翻译： 根据本发明的半导体器件具有多层布线结构，其层叠并设置多个夹着绝缘膜的多层布线结构，并且包括：以铜为主要成分的铜线; 形成在铜线上的绝缘膜; 铝线，其以铝为主要成分，并形成在所述绝缘膜上，以通过形成为穿透所述绝缘膜的通孔与所述铜线电连接; 和形成在铝线上的表面保护膜; 并且所述表面保护膜形成有用于使铝线的一部分暴露于与外部部分电连接的电极焊盘的焊盘开口。

公开(公告)号：US20080122094A1

公开(公告)日：2008-05-29

申请号：US11945766

申请日：2007-11-27

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L23/532 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed metallic element. After this coating with the alloy film, a copper film is laminated on the insulating film to fill up the wiring trench. Then, unnecessary portions of the copper film outside the wiring trench are removed, so that the surface of the copper film remaining in the wiring trench is generally flush with the surface of the insulating film. Thereafter heat treatment is performed. The prescribed metallic element is deposited on the wiring trench due to this heat treatment. Then, the prescribed metallic element deposited on the wiring trench is removed.

摘要翻译： 在制造本发明的半导体器件的方法中，在绝缘膜的表面上形成布线沟槽，然后用由含铜的合金材料制成的合金膜涂覆该布线沟槽的内表面， 规定的金属元素。 在用合金膜涂覆之后，在绝缘膜上层压铜膜以填充布线沟槽。 然后，除去布线沟槽外部的铜膜的不必要部分，使得残留在布线沟槽中的铜膜的表面与绝缘膜的表面大致齐平。 然后进行热处理。 由于这种热处理，规定的金属元素沉积在布线沟槽上。 然后，去除沉积在布线沟槽上的规定金属元素。

公开(公告)号：US08981440B2

公开(公告)日：2015-03-17

申请号：US13119070

申请日：2009-09-16

申请人： Yuichi Nakao

发明人： Yuichi Nakao

IPC分类号： H01L21/02 ,  H01L49/02 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

摘要： A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.

摘要翻译： 本发明的半导体存储元件的制造方法是具有下电极，强电介质膜和上电极的强电介质电容器的半导体存储元件的制造方法，其特征在于，包括： 金属插塞和绝缘层中的第二金属插塞; 形成覆盖层的步骤，所述覆盖层至少覆盖与所述第一金属插塞电接触的固定的所述第二金属插塞; 在形成覆盖层之后，依次沉积下电极材料，铁电薄膜材料和上电极材料，形成沉积结构的步骤; 以及通过蚀刻除去所述沉积结构的一部分以外的其它部分使得所述沉积结构的所述部分保留在所述第一金属插塞上而形成所述强电介质电容器的步骤。

公开(公告)号：US08912657B2

公开(公告)日：2014-12-16

申请号：US12801933

申请日：2010-07-02

申请人： Yuichi Nakao ,  Satoshi Kageyama ,  Masaru Naitou

发明人： Yuichi Nakao ,  Satoshi Kageyama ,  Masaru Naitou

IPC分类号： H01L29/72 ,  B23D51/12

CPC分类号： H01L23/528 ,  B23D51/125 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079

摘要： The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，层叠在半导体衬底上的第一绝缘层，嵌入在第一绝缘层的引线形成区域中的第一金属布线图案，层压在第一绝缘层上的第二绝缘层 层，嵌入在第二绝缘层的线形成区域中的第二金属布线图案和嵌入在与第二绝缘层的线形成区域相对的线对向区域中的第一虚拟金属图案，并且以非线 与第二绝缘层的线形成区域以外的非线形成区域相对的相对区域，线对向区域和非线对置区域各自位于除非线形成区域以外的非线形成区域 第一绝缘层的线形成区域。

公开(公告)号：US08102051B2

公开(公告)日：2012-01-24

申请号：US12452235

申请日：2008-06-20

申请人： Yuichi Nakao

发明人： Yuichi Nakao

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/53295 ,  C23C16/402 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).

摘要翻译： 根据本发明的半导体器件包括由包含Si和O的材料制成的第一绝缘层，通过挖掘第一绝缘层而形成的凹槽，嵌入凹槽中的嵌入体，其由主要由 Cu，第二绝缘层，堆叠在由包含Si和O的材料制成的第一绝缘层和嵌入体上，以及阻挡膜，形成在嵌入体与第一绝缘层和第二绝缘层中的每一个之间， 由MnxSiyOz（x，y和z：数字大于零）组成。