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    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
    1.
    发明申请
    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE 有权
    用于在半导体器件上镀膜特征的熔断母线

    公开(公告)号：US20130020674A1

    公开(公告)日：2013-01-24

    申请号：US13189060

    申请日：2011-07-22

    申请人： GEORGE R. LEAL ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： GEORGE R. LEAL ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L23/525

    CPC分类号： H01L23/585 ,  H01L22/32 ,  H01L23/5256 ,  H01L2224/02166

    摘要： A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

    摘要翻译： 半导体结构包括半导体衬底; 在衬底中形成的半导体器件; 半导体器件上的多个互连层; 在所述多个互连层的顶表面上的互连焊盘，其中所述互连焊盘通过所述多个互连层耦合到所述半导体器件; 围绕所述半导体器件并从所述衬底垂直延伸到所述多个互连层的顶表面的连续密封环; 以及联接在所述互连焊盘和所述密封环之间的熔丝，其中所述熔丝处于非导电状态。

    Fused buss for plating features on a semiconductor die
    2.
    发明授权
    Fused buss for plating features on a semiconductor die 有权
    熔融母线用于半导体管芯上的电镀特征

    公开(公告)号：US08368172B1

    公开(公告)日：2013-02-05

    申请号：US13189060

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L23/525

    CPC分类号： H01L23/585 ,  H01L22/32 ,  H01L23/5256 ,  H01L2224/02166

    摘要： A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

    摘要翻译： 半导体结构包括半导体衬底; 在衬底中形成的半导体器件; 半导体器件上的多个互连层; 在所述多个互连层的顶表面上的互连焊盘，其中所述互连焊盘通过所述多个互连层耦合到所述半导体器件; 围绕所述半导体器件并从所述衬底垂直延伸到所述多个互连层的顶表面的连续密封环; 以及联接在所述互连焊盘和所述密封环之间的熔丝，其中所述熔丝处于非导电状态。

    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
    3.
    发明申请
    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE 有权
    用于在半导体器件上镀膜特征的熔断母线

    公开(公告)号：US20130023091A1

    公开(公告)日：2013-01-24

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Fused buss for plating features on a semiconductor die
    4.
    发明授权
    Fused buss for plating features on a semiconductor die 有权
    熔融母线用于半导体管芯上的电镀特征

    公开(公告)号：US08349666B1

    公开(公告)日：2013-01-08

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82 ,  H01L21/332 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Scribe street structure for backend interconnect semiconductor wafer integration
    5.
    发明授权
    Scribe street structure for backend interconnect semiconductor wafer integration 有权
    Scribe街道结构用于后端互连半导体晶片集成

    公开(公告)号：US07129566B2

    公开(公告)日：2006-10-31

    申请号：US10880681

    申请日：2004-06-30

    申请人： Trent S. Uehling ,  Kevin J. Hess

    发明人： Trent S. Uehling ,  Kevin J. Hess

    IPC分类号： H01L23/544

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality. A separation structure that includes metal is located in the interconnect structure. At least a portion of the separation structure is located in a saw kerf of the street. The separation structure is arranged to provide a predefined separation path for separating the first die area during a singulation process.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成具有衬底和互连结构的晶片。 晶片还包括多个管芯区域和位于多个第一管芯区域和多个第二管芯区域之间的街道。 包括金属的分离结构位于互连结构中。 分离结构的至少一部分位于街道的锯切区域中。 分离结构被布置成提供用于在分割过程期间分离第一管芯区域的预定分离路径。

    Semiconductor wafer plating bus and method for forming
    9.
    发明授权
    Semiconductor wafer plating bus and method for forming 有权
    半导体晶圆电镀母线及成型方法

    公开(公告)号：US08895409B2

    公开(公告)日：2014-11-25

    申请号：US13948927

    申请日：2013-07-23

    申请人： Trent S. Uehling

    发明人： Trent S. Uehling

    IPC分类号： H01L21/301 ,  H01L21/445 ,  H01L23/58 ,  H01L21/768 ,  H01L23/00

    CPC分类号： H01L21/76838 ,  H01L23/585 ,  H01L24/05

    摘要： A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

    摘要翻译： 半导体晶片包括模具，边缘密封件，接合焊盘，电镀母线和迹线。 模具毗邻锯街。 边缘密封沿着管芯的周边，并且包括形成在管芯的最后互连层中的导电层。 接合焊盘形成为最后互连层或最后互连层的一部分上方的金属沉积层的一部分。 电镀巴士在锯街内。 轨迹连接到边缘密封上的接合焊盘和电镀母线（1），与边缘密封绝缘，并形成在金属沉积层中，或（2）通过边缘密封并与边缘密封绝缘。