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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08885380B2

    公开(公告)日：2014-11-11

    申请号：US13209026

    申请日：2011-08-12

    申请人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

    发明人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

    IPC分类号： G11C5/02 ,  H01L25/18 ,  G11C7/10

    CPC分类号： H01L25/18 ,  G11C5/02 ,  G11C7/10 ,  H01L2224/48091 ,  H01L2225/06544 ,  H01L2924/00014

    摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.

    摘要翻译： 公开了半导体封装。 半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。 封装接口包括至少第一对端子。 每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。 接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个 通过衬底通孔的堆叠。

    Semiconductor device capable of adjusting memory page size based on a row address and a bank address
    4.
    发明授权
    Semiconductor device capable of adjusting memory page size based on a row address and a bank address 有权
    能够根据行地址和银行地址来调整存储器页面大小的半导体器件

    公开(公告)号：US08411528B2

    公开(公告)日：2013-04-02

    申请号：US12684497

    申请日：2010-01-08

    申请人： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

    发明人： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

    IPC分类号： G11C8/12

    CPC分类号： G11C8/10 ,  G11C5/00 ,  G11C5/02 ,  G11C8/06 ,  G11C8/12

    摘要： A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    摘要翻译： 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分，以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 有权
    记忆系统

    公开(公告)号：US20130058145A1

    公开(公告)日：2013-03-07

    申请号：US13604308

    申请日：2012-09-05

    申请人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

    发明人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

    IPC分类号： G11C29/00 ,  G11C15/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/783 ,  G11C2029/0409 ,  G11C2029/4402

    摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

    摘要翻译： 半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

    BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM
    6.
    发明申请
    BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM 有权
    内存设备或系统中的页面管理

    公开(公告)号：US20130055048A1

    公开(公告)日：2013-02-28

    申请号：US13570568

    申请日：2012-08-09

    申请人： HAK-SOO YU ,  CHUL-WOO PARK ,  UK-SONG KANG ,  JOO-SUN CHOI ,  HONG-SUN HWANG ,  JONG-PIL SON

    发明人： HAK-SOO YU ,  CHUL-WOO PARK ,  UK-SONG KANG ,  JOO-SUN CHOI ,  HONG-SUN HWANG ,  JONG-PIL SON

    IPC分类号： G11C29/04 ,  G06F11/16

    CPC分类号： G11C29/24 ,  G11C29/00 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

    摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

    摘要翻译： 存储器件包括存储单元阵列和坏页映射。 存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。 坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。 根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

    MEMORY DEVICE FOR MANAGING TIMING PARAMETERS
    7.
    发明申请
    MEMORY DEVICE FOR MANAGING TIMING PARAMETERS 有权
    用于管理时序参数的存储器件

    公开(公告)号：US20130039135A1

    公开(公告)日：2013-02-14

    申请号：US13569636

    申请日：2012-08-08

    申请人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

    发明人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

    IPC分类号： G11C7/22

    CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

    摘要： A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

    摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

    Inter-transmission multi memory chip, system including the same and associated method
    10.
    发明授权
    Inter-transmission multi memory chip, system including the same and associated method 有权
    传输多内存芯片，系统包括相同和相关的方法

    公开(公告)号：US07855925B2

    公开(公告)日：2010-12-21

    申请号：US12071745

    申请日：2008-02-26

    申请人： Uk-song Kang ,  Jung-bae Lee

    发明人： Uk-song Kang ,  Jung-bae Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C5/025 ,  G11C5/04

    摘要： A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.

    摘要翻译： 堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。