公开(公告)号：US20140078832A1

公开(公告)日：2014-03-20

申请号：US13615723

申请日：2012-09-14

申请人： TAKAO AKAOGI ,  YIDER WU ,  YI-HSIU CHEN ,  HUNG-HUI LAI

发明人： TAKAO AKAOGI ,  YIDER WU ,  YI-HSIU CHEN ,  HUNG-HUI LAI

IPC分类号： H01L27/105 ,  H01L21/336 ,  G11C16/06

CPC分类号： H01L27/11565 ,  H01L21/76229 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/11568

摘要： A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

摘要翻译： 引入具有离散隔离结构和SONOS存储单元的非易失性存储器，其操作方法及其制造方法。 具有阵列区域的半导体衬底上的每个隔离结构具有多个间隙，以便形成离散的隔离结构，从而将源极线注入到半导体衬底的间隙中。 由于源极线不被隔离结构切断，所以不连接到源极线的所需量的栅极极大地减小，从而减小了非易失性存储器中的栅极引脚所需的空间。

公开(公告)号：US20140030860A1

公开(公告)日：2014-01-30

申请号：US13556490

申请日：2012-07-24

申请人： YIDER WU ,  YI-HSIU CHEN ,  WEN-CHENG LEE

发明人： YIDER WU ,  YI-HSIU CHEN ,  WEN-CHENG LEE

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/66825

摘要： A manufacturing method of tunnel oxide of NOR flash memory controls the temperature and thickness of tunnel oxide in a gate structure to prevent a channel region to change its doping concentration and range due to a high-temperature manufacturing process, so as to overcome the leakage current and improve the reliability of storing data.

摘要翻译： NOR闪存的隧道氧化物的制造方法控制栅极结构中的隧道氧化物的温度和厚度，以防止沟道区域由于高温制造工艺而改变其掺杂浓度和范围，从而克服漏电流 并提高存储数据的可靠性。

公开(公告)号：US20130093098A1

公开(公告)日：2013-04-18

申请号：US13272506

申请日：2011-10-13

申请人： Ku-Feng YANG ,  Tsang-Jiuh WU ,  Yi-Hsiu CHEN ,  Ebin LIAO ,  Yuan-Hung LIU ,  Wen-Chih CHIOU

发明人： Ku-Feng YANG ,  Tsang-Jiuh WU ,  Yi-Hsiu CHEN ,  Ebin LIAO ,  Yuan-Hung LIU ,  Wen-Chih CHIOU

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

摘要翻译： 形成通过（TSV）通孔的结构的实施例能够降低由于层间电介质层（ILD）层的过度抛光而损坏栅极结构的风险。 在一端附近具有较宽开口的TSV结构还可实现更好的间隙填充。

公开(公告)号：US20100227460A1

公开(公告)日：2010-09-09

申请号：US12399377

申请日：2009-03-06

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/76224

摘要： In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

摘要翻译： 在制造NOR闪速存储器的方法中，当存储器件尺寸进一步减小时，省略在栅极结构的两个侧面处形成间隔物，并且两个栅极结构之间的间隔可以直接用介电间隔件 或浅沟槽隔离（STI）层。 因此，可以避免在栅极结构之间的极小空间中形成间隔物而造成存储器件制造难度增大的问题。 该方法还能够省略形成硅化物层所需的自对准步骤。 因此，也可以避免由于栅极结构之间的极小空间而导致的自对准难度。

公开(公告)号：US20100099262A1

公开(公告)日：2010-04-22

申请号：US12254022

申请日：2008-10-20

申请人： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

发明人： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

IPC分类号： H01L21/3105

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/976

摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

摘要翻译： 在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层 门。 通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。 同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

公开(公告)号：US20100230738A1

公开(公告)日：2010-09-16

申请号：US12400828

申请日：2009-03-10

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/00

CPC分类号： H01L27/11521 ,  H01L29/40114 ,  H01L29/42324

摘要： In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

摘要翻译： 在制造NOR闪速存储器结构的方法中，执行高掺杂离子注入工艺以形成与轻掺杂漏极区重叠的高度掺杂的漏极区。 因此，在用于形成接触孔的蚀刻工艺期间，闪速存储器结构可以具有减小的漏极结深度以改善短沟道效应，同时保护轻掺杂漏极区域不被穿孔。

公开(公告)号：US20120067506A1

公开(公告)日：2012-03-22

申请号：US13212031

申请日：2011-08-17

申请人： Yi-Hun Tan ,  Po-Tung Lai ,  Yi-Hsiu Chen

发明人： Yi-Hun Tan ,  Po-Tung Lai ,  Yi-Hsiu Chen

IPC分类号： B32B37/00 ,  B29C65/00

CPC分类号： B29C55/026 ,  B29C35/041 ,  B29C55/06 ,  B29C65/48 ,  B29C65/483 ,  B29C66/45 ,  B29C66/71 ,  B29C66/7338 ,  B29C66/83413 ,  B29C2035/042 ,  B29C2795/002 ,  B29K2029/04 ,  B29K2105/0032 ,  B29K2105/24 ,  B29K2995/0034 ,  B32B2037/243 ,  B32B2038/0028 ,  G02B5/3033

摘要： A film processing equipment and a method for processing a film is provided. A feeding roller feeds the film to a swelling bath and the swelling bath immerses the film. A dyeing bath dyes the film transferred from the swelling bath and a stretching bath stretches the film. The stretching bath comprises three sets of rollers dividing a film transferring path into a first interval length and a second interval length. The first interval length is in an upstream with respect to the film transferring path and smaller than the second interval length. A crosslinking bath performs a crosslinking process on the film transferred from the stretching bath and a washing bath washes the film. A film attaching assembly performs a film attaching process on the film transferred from the washing bath and a winding device winds the film transferred from the film attaching assembly.

摘要翻译： 提供了一种胶片处理设备和一种处理胶片的方法。 进料辊将膜送入溶胀浴中，并且溶胀浴浸渍该膜。 染色浴染色从溶胀浴转移的膜，拉伸浴使膜延伸。 拉伸浴包括将胶片传送路径分成第一间隔长度和第二间隔长度的三组辊。 第一间隔长度相对于胶片传送路径处于上游，并且小于第二间隔长度。 交联浴对从拉伸浴转移的膜进行交联处理，洗涤浴洗涤该膜。 胶片安装组件对从洗涤槽传送的胶片进行胶片贴附过程，并且缠绕装置卷绕从胶片安装组件传送的胶片。

公开(公告)号：US08803322B2

公开(公告)日：2014-08-12

申请号：US13272506

申请日：2011-10-13

申请人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

摘要翻译： 形成通过（TSV）通孔的结构的实施例能够降低由于层间电介质层（ILD）层的过度抛光而损坏栅极结构的风险。 在一端附近具有较宽开口的TSV结构还可实现更好的间隙填充。

公开(公告)号：US08158519B2

公开(公告)日：2012-04-17

申请号：US12254022

申请日：2008-10-20

申请人： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

发明人： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/976

摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

摘要翻译： 在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层 门。 通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。 同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

公开(公告)号：US20100171161A1

公开(公告)日：2010-07-08

申请号：US12350298

申请日：2009-01-08

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L29/788 ,  H01L29/00 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

摘要翻译： 在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。 因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。