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    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    1.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220392882A1

    公开(公告)日：2022-12-08

    申请号：US17891444

    申请日：2022-08-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

    INSTRUCTION CONTEXT SWITCHING
    3.
    发明申请
    INSTRUCTION CONTEXT SWITCHING 有权
    指令语境切换

    公开(公告)号：US20160371082A1

    公开(公告)日：2016-12-22

    申请号：US14746601

    申请日：2015-06-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

    IPC: G06F9/30

    CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

    Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.

    Abstract translation: 处理装置包括包括上下文缓冲器的第一存储器。 处理设备还包括处理器核心，用于基于存储在处理器核心的寄存器中的上下文信息来执行线程，以及存储器控制器，用于基于上下文缓冲器和寄存器的一个或多个延迟来选择性地移动上下文信息的子集 线程。

    Offset-aligned three-dimensional integrated circuit
    4.
    发明授权
    Offset-aligned three-dimensional integrated circuit 有权

    公开(公告)号：US11437359B2

    公开(公告)日：2022-09-06

    申请号：US16799243

    申请日：2020-02-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

    Extreme-bandwidth scalable performance-per-watt GPU architecture
    5.
    发明授权
    Extreme-bandwidth scalable performance-per-watt GPU architecture 有权

    公开(公告)号：US10509596B2

    公开(公告)日：2019-12-17

    申请号：US15851476

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Dmitri Yudanov ,  Jiasheng Chen

    IPC: G06F3/00 ,  G06F3/06 ,  G06T1/60 ,  G06T1/20 ,  G06F9/38

    Abstract: A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

    METHOD AND APPARATUS OF INTEGRATING MEMORY STACKS
    6.
    发明申请
    METHOD AND APPARATUS OF INTEGRATING MEMORY STACKS 审中-公开

    公开(公告)号：US20180341613A1

    公开(公告)日：2018-11-29

    申请号：US15605291

    申请日：2017-05-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Dmitri Yudanov ,  Michael Ignatowski

    IPC: G06F13/40 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C5/14

    Abstract: A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

    Dynamic wavefront creation for processing units using a hybrid compactor
    8.
    发明授权
    Dynamic wavefront creation for processing units using a hybrid compactor 有权

    公开(公告)号：US09898287B2

    公开(公告)日：2018-02-20

    申请号：US14682971

    申请日：2015-04-09

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sooraj Puthoor ,  Bradford M. Beckmann ,  Dmitri Yudanov

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

    CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46

    Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.

    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    10.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190326272A1

    公开(公告)日：2019-10-24

    申请号：US15958169

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

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