公开(公告)号：US20170102899A1

公开(公告)日：2017-04-13

申请号：US15385429

申请日：2016-12-20

Applicant: APPLE INC.

Inventor： Daniel J. Post ,  Matthew J. Byom ,  Vadim Khmelnitsky ,  Nir Jacob Wakrat ,  Kenneth L. Herman

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C29/52

Abstract: Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

公开(公告)号：US09690953B2

公开(公告)日：2017-06-27

申请号：US14212049

申请日：2014-03-14

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Matthew J. Byom ,  Alexander C. Sanks ,  Daniel J. Post ,  Hari Hara Kumar Maharaj ,  Nir Jacob Wakrat ,  Kenneth L. Herman

IPC: G06F21/00 ,  G06F21/79

CPC classification number: G06F21/79 ,  G06F2221/2107

Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.

公开(公告)号：US09383808B2

公开(公告)日：2016-07-05

申请号：US14448085

申请日：2014-07-31

Applicant: Apple Inc.

Inventor： Nir J. Wakrat ,  Kenneth L. Herman ,  Matthew J. Byom

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126

Abstract: Systems and methods are disclosed for dynamically allocating power for a system having non-volatile memory. A power budgeting manager of a system can determine if the total amount of power available for the system is below a pre-determined power level (e.g., a low power state). While the system is operating in the low power state, the power budgeting manager can dynamically allocate power among various components of the system (e.g., a processor and non-volatile memory).

Abstract translation: 公开了用于为具有非易失性存储器的系统动态分配功率的系统和方法。 系统的功率预算管理器可以确定系统可用的总功率是否低于预定功率电平（例如，低功率状态）。 当系统工作在低功率状态时，功率预算管理器可以在系统的各个组件（例如，处理器和非易失性存储器）之间动态分配功率。

公开(公告)号：US20140344609A1

公开(公告)日：2014-11-20

申请号：US14448085

申请日：2014-07-31

Applicant: Apple Inc.

Inventor： Nir J. Wakrat ,  Kenneth L. Herman ,  Matthew J. Byom

IPC: G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126

Abstract: Systems and methods are disclosed for dynamically allocating power for a system having non-volatile memory. A power budgeting manager of a system can determine if the total amount of power available for the system is below a pre-determined power level (e.g., a low power state). While the system is operating in the low power state, the power budgeting manager can dynamically allocate power among various components of the system (e.g., a processor and non-volatile memory).

Abstract translation: 公开了用于为具有非易失性存储器的系统动态分配功率的系统和方法。 系统的功率预算管理器可以确定系统可用的总功率是否低于预定功率电平（例如，低功率状态）。 当系统工作在低功率状态时，功率预算管理器可以在系统的各个组件（例如，处理器和非易失性存储器）之间动态分配功率。

公开(公告)号：US09841917B2

公开(公告)日：2017-12-12

申请号：US14962339

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Vadim Khmelnitsky ,  Daniel J. Post ,  Nir Jacob Wakrat ,  Matthew J. Byom ,  Kenneth L. Herman ,  Alexander C. Sanks

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206

Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

公开(公告)号：US20160092110A1

公开(公告)日：2016-03-31

申请号：US14962339

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Vadim Khmelnitsky ,  Daniel J. Post ,  Nir Jacob Wakrat ,  Matthew J. Byom ,  Kenneth L. Herman ,  Alexander C. Sanks

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206

Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

Abstract translation: 公开了用于配置非易失性存储器（“NVM”）的系统和方法。 在一些实施例中，NVM的每个块可以包括可以被编码（例如，游程长度编码）和动态尺寸的块内容表（“TOC”）。 因此，当用户数据被编程到块时，块TOC的大小可以被同时重新计算并且仅在必要时增加。 在一些实施例中，NVM接口可以使用存储在上下文信息中的编织序列和与块的每个页面相关联的至少一个编织序列来确定在系统启动之后跨块的页面是否重播。

公开(公告)号：US20140281588A1

公开(公告)日：2014-09-18

申请号：US14212049

申请日：2014-03-14

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Matthew J. Byom ,  Alexander C. Sanks ,  Daniel J. Post ,  Hari Hara Kumar Maharaj ,  Nir Jacob Wakrat ,  Kenneth L. Herman

IPC: H04L9/08

CPC classification number: G06F21/79 ,  G06F2221/2107

Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.

Abstract translation: 公开了用于为具有非易失性存储器（“NVM”）的系统生成有效读取的系统和方法。 读取命令可以由系统的主机处理器分成两个阶段：a）将命令发送到系统的存储处理器，其中命令与一个或多个逻辑地址相关联，以及b）生成数据传输信息。 主机处理器可以在存储处理器正在处理来自主机处理器的命令时产生数据传输信息。 一旦生成了数据传输信息，并且已经从NVM读取了数据，则可以传送数据。

公开(公告)号：US20140192599A1

公开(公告)日：2014-07-10

申请号：US14204162

申请日：2014-03-11

Applicant: Apple Inc.

Inventor： Matthew J. Byom ,  Nir J. Wakrat ,  Kenneth L. Herman

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C16/04 ,  G11C29/08 ,  G11C29/12 ,  G11C2029/1206

Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Abstract translation: 提供了系统和方法来测试诸如闪存之类的非易失性存储器。 非易失性存储器可以被虚拟地分割成测试区域和通用区域。 测试应用可以存储在通用区域中，并且可以执行测试应用以对测试区域中的存储器位置进行测试。 测试结果可以存储在通用区域中。 在测试完成时，测试结果可以从通用区域提供并显示给用户。 虚拟分区可以在运送电子设备以进行分发之前被移除。

公开(公告)号：US20140075208A1

公开(公告)日：2014-03-13

申请号：US14082940

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Kenneth L. Herman ,  Matthew J. Byom ,  Michael J. Smith ,  Tahoma M. Toelkes

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F21/72 ,  G06F21/79 ,  G06F2221/2107 ,  G11C16/10 ,  G11C16/22

Abstract: Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues.

Abstract translation: 提供了用于白化和管理数据以存储在诸如闪存的非易失性存储器中的系统，装置和方法。 在一些实施例中，提供诸如媒体播放器的电子设备，其可以包括片上系统（SoC）和非易失性存储器。 SoC可以包括SoC控制电路和用作SoC控制电路和非易失性存储器之间的接口的存储器接口。 SoC还可以包括加密模块，例如基于高级加密标准（AES）的块密码。 存储器接口可以指示加密模块在存储在非易失性存储器之前对所有类型的数据进行白化，包括敏感数据，非敏感数据和存储器管理数据。 这可以例如防止或减少程序干扰问题或其他读/写/擦除可靠性问题。

公开(公告)号：US20130212318A1

公开(公告)日：2013-08-15

申请号：US13725671

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Tahoma Toelkes ,  Nir Jacob Wakrat ,  Kenneth L. Herman ,  Barry Corlett ,  Vadim Khmelnitsky ,  Anthony Fai ,  Daniel Jeffrey Post ,  Hsiao Thio

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/7208

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Abstract translation: 所公开的架构使用地址映射将主机接口上的块地址映射到非易失性存储器（NVM）设备的内部块地址。 块地址映射到用于选择由块地址标识的可并行寻址单元（CAU）的内部芯片选择。 所公开的架构支持用于读取，写入，擦除和获取状态操作的通用NVM命令。 该架构还支持扩展命令集，以支持利用多个CAU架构的读写操作。