公开(公告)号：US20030216037A1

公开(公告)日：2003-11-20

申请号：US10409406

申请日：2003-04-07

申请人： Applied Materials, Inc.

发明人： Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  John C. Forster ,  Jick M. Yu

IPC分类号： C23C014/00 ,  C23C014/32 ,  H01L021/4763

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/185 ,  C23C14/5873 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76865

摘要： A first method is provided for forming a barrier layer on a substrate by sputter-depositing a tantalum nitride layer on a substrate having (1) a metal feature formed on the substrate; (2) a dielectric layer formed over the metal feature; and (3) a via formed in the dielectric layer so as to expose the metal feature. The via has side walls and a bottom, and a width of about 0.18 microns or less. The tantalum nitride layer is deposited on the side walls and bottom of the via and on a field region of the dielectric layer; and has a thickness of at least about 200 angstroms on the field region. The first method also includes sputter-depositing a tantalum layer on the substrate, in the same chamber. The tantalum layer having a thickness of less than about 100 angstroms on the field region. Other aspects are provided.

摘要翻译： 提供了第一种方法，用于通过在（1）形成在基底上的金属特征的衬底上溅射沉积氮化钽层，在衬底上形成阻挡层; （2）形成在所述金属特征上的电介质层; 和（3）形成在电介质层中的通孔以暴露金属特征。 通孔具有侧壁和底部，宽度为约0.18微米或更小。 氮化钽层沉积在通孔的侧壁和底部以及电介质层的场区上; 并且在场区域具有至少约200埃的厚度。 第一种方法还包括在相同的室中在衬底上溅射沉积钽层。 该钽层的厚度在场区域上小于约100埃。 提供其他方面。

公开(公告)号：US20020102842A1

公开(公告)日：2002-08-01

申请号：US10074938

申请日：2002-02-11

申请人： Applied Materials, Inc.

发明人： Roderick Craig Mosley ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yun Chen

IPC分类号： H01L021/44 ,  H01L021/4763

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

公开(公告)号：US20020029958A1

公开(公告)日：2002-03-14

申请号：US09886439

申请日：2001-06-20

申请人： Applied Materials, Inc.

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： C23C014/00 ,  C23C014/32

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US20030082301A1

公开(公告)日：2003-05-01

申请号：US10199415

申请日：2002-07-18

申请人： Applied Materials, Inc.

发明人： Ling Chen ,  Hua Chung ,  Barry L. Chin ,  Hong Zhang

IPC分类号： C23C016/00 ,  B05D001/36

CPC分类号： H01L21/28562 ,  C23C16/34 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45504 ,  C23C16/45508 ,  C23C16/45512 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/45563 ,  C23C16/45582 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76871

摘要： A method for depositing a refractory metal nitride barrier layer having a thickness of about 20 angstroms or less is provided. In one aspect, the refractory metal nitride layer is formed by introducing a pulse of a metal-containing compound followed by a pulse of a nitrogen-containing compound. The refractory metal nitride barrier layer provides adequate barrier properties and allows the grain growth of the first metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.

摘要翻译： 提供了一种沉积具有约20埃或更小厚度的难熔金属氮化物阻挡层的方法。 一方面，难熔金属氮化物层是通过引入含金属化合物的脉冲，随后是含氮化合物的脉冲而形成的。 难熔金属氮化物阻挡层提供了足够的阻挡性能，并且允许第一金属层的晶粒生长继续穿过阻挡层进入第二金属层，从而增强了互连的电性能。

公开(公告)号：US20040222082A1

公开(公告)日：2004-11-11

申请号：US10429941

申请日：2003-05-05

申请人： APPLIED MATERIALS, INC.

发明人： Praburam Gopalraja ,  Xianmin Tang ,  Jianming Fu ,  Mark A. Perrin ,  Jean Yue (Phillip) Wang ,  Arvind Sundarrajan ,  Hong Zhang ,  Jick Yu ,  Umesh Kelkar ,  Zheng Xu ,  Fusen Chen

IPC分类号： C23C014/32 ,  G21G005/00

CPC分类号： H01J37/34 ,  C23C14/046 ,  C23C14/3442 ,  C23C14/5833 ,  H01J37/3053 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865

摘要： In conjunction with sputtering a metal, especially copper, into high aspect-ratio holes in a wafer, an oblique ion milling method in which argon ions or other particles having energies in the range of 200 to 1500 eV are directed to the wafer at between 10 and 35null to the wafer surface to sputter etch material sputter deposited preferentially on the upper corners of the holes. The milling may be performed in the sputter deposition chamber either simultaneously with the deposition or after it or performed afterwards in a separate milling reactor. A plurality of ion sources arranged around the chamber improve angular uniformity or arranged axially improve radial uniformity or vary the angle of incidence. An annular ion source about the chamber axis allows a plasma current loop. Anode layer ion sources and sources composed of copper are advantageous.

摘要翻译： 结合将金属，特别是铜溅射到晶片中的高纵横比孔中，其中具有在200至1500eV范围内的能量的氩离子或其它颗粒的倾斜离子研磨方法在10 并且与晶片表面成35°的溅射蚀刻材料溅射沉积优先在孔的上角上。 铣削可以在溅射沉积室中同时进行沉积，或在其之后或之后在单独的研磨反应器中进行。 围绕腔室布置的多个离子源提高了角度均匀性或者轴向地改变径向均匀性或改变入射角。 围绕腔室轴线的环形离子源允许等离子体电流回路。 阳极层离子源和由铜组成的源是有利的。