公开(公告)号：US5084402A

公开(公告)日：1992-01-28

申请号：US353060

申请日：1989-05-17

申请人： Akihisa Uchida ,  Daisuke Okaka ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

发明人： Akihisa Uchida ,  Daisuke Okaka ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

公开(公告)号：US5200348A

公开(公告)日：1993-04-06

申请号：US801865

申请日：1991-12-03

申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

公开(公告)号：US4853343A

公开(公告)日：1989-08-01

申请号：US169748

申请日：1988-03-18

申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

公开(公告)号：US4746963A

公开(公告)日：1988-05-24

申请号：US946778

申请日：1986-12-29

申请人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

发明人： Akihisa Uchida ,  Daisuke Okada ,  Toshihiko Takakura ,  Katsumi Ogiue ,  Yoichi Tamaki ,  Masao Kawamura

IPC分类号： H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/73 ,  H01L21/95

CPC分类号： H01L21/76224 ,  H01L21/76 ,  H01L21/76202 ,  H01L21/763 ,  H01L2924/0002 ,  Y10S438/981

摘要： A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

摘要翻译： 公开了一种采用新的隔离工艺的半导体器件，其中隔离区域是通过各向异性干法蚀刻将掩埋材料埋入形成在半导体主体中的宽度基本恒定的深沟槽的区域，半导体元件形成为选定的 通过隔离区域隔离的半导体区域以及其中没有形成半导体元件的其它半导体区域，其全部表面被由半导体本体的局部氧化产生的厚氧化膜覆盖。 新的隔离工艺非常适用于双极型半导体器件，其中深沟形成为通过N +型掩埋层到达半导体衬底，并且与上述厚氧化膜隔离物同时形成的厚氧化膜 双极晶体管的基极区域和集电极接触区域。

公开(公告)号：US5141888A

公开(公告)日：1992-08-25

申请号：US642922

申请日：1991-01-18

申请人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

发明人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/732

CPC分类号： H01L21/763 ,  H01L21/76224 ,  H01L29/7325 ,  Y10S148/05

摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

公开(公告)号：US4819054A

公开(公告)日：1989-04-04

申请号：US11932

申请日：1987-02-06

申请人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

发明人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/732 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76224 ,  H01L29/7325 ,  Y10S148/05

摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

摘要翻译： 双极型半导体集成电路器件设置有通过切割半导体本体的主表面以在双极晶体管之间形成隔离区而形成的U形沟槽。 可以通过热氧化在U形槽中形成氧化硅膜，同时形成用于在每个集电极接触区域和基极区域之间形成隔离区域的氧化硅膜。 在集电极接触区域和基极区域之间形成氧化硅膜不需要单独的步骤。 可以控制氧化硅膜的厚度，并且即使在其两个边缘，即与U形槽的边界处，也具有足够的厚度，使得双极晶体管表现出良好的电特性。 也就是说，其集电极电阻不增加，并且集电极区域和基极区域之间的pn结处的击穿电压不降低。 U形槽可以各自包括窄的和深的子槽，其中形成在子槽的表面上的厚的氧化膜和形成在子槽之间的区域的表面上的厚氧化膜，并且形成有布线 在子槽之间的区域上的氧化物上。

公开(公告)号：US5011788A

公开(公告)日：1991-04-30

申请号：US284557

申请日：1988-12-15

申请人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

发明人： Mikinori Kawaji ,  Toshihiko Takakura ,  Akihisa Uchida ,  Shigeo Kuroda ,  Yoichi Tamaki ,  Takeo Shiba ,  Kazuhiko Sagara ,  Masao Kawamura

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/732

CPC分类号： H01L21/763 ,  H01L21/76224 ,  H01L29/7325 ,  Y10S148/05

摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

公开(公告)号：US4949162A

公开(公告)日：1990-08-14

申请号：US201928

申请日：1988-06-03

申请人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

发明人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/02 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/05042 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

摘要翻译： 一种多层半导体集成电路，其具有多个布线层，其中至少在布置在栅格中的布线沟道区上的下层的布线延伸。 虚拟基座由与形成下层的线相同的导电层形成，并且布置在布线沟道区域的相交区域中，其中没有放置下层的线。 一种制造这样的半导体集成电路的方法包括以下步骤：制备用于在布线沟道区域的所有交叉区域中布置虚设基座的虚拟基座布局数据和用于在预定布线通道上形成下层的线的线路布局数据 布线通道区域，并且通过逻辑和（OR）组合虚拟基座布局数据和线路布局数据。

公开(公告)号：US4729965A

公开(公告)日：1988-03-08

申请号：US855616

申请日：1986-04-09

申请人： Yoichi Tamaki ,  Kazuhiko Sagara ,  Norio Hasegawa ,  Shinji Okazaki ,  Toshihiko Takakura ,  Hirotaka Nishizawa

发明人： Yoichi Tamaki ,  Kazuhiko Sagara ,  Norio Hasegawa ,  Shinji Okazaki ,  Toshihiko Takakura ,  Hirotaka Nishizawa

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L27/12 ,  H01L21/265

CPC分类号： H01L21/033 ,  H01L21/28525 ,  H01L29/0804 ,  Y10S438/98

摘要： This invention relates to a method of producing a semiconductor device which is suitable for forming a bipolar transistor having less fluctuation of characteristics at a high production yield.In accordance with the present invention, a graft base (or an extrinsic base) 20 is formed by doping an impurity from a polycrystalline silicon film 13, while an emitter is formed by lithographic technique.Since the emitter is formed by lithographic technique, the position at which the emitter is to be formed unavoidably changes at the time of mask alignment, but its influence upon transistor characteristics is negligible. Therefore, bipolar transistors having far more uniform characteristics can be formed far more easily than with the method which forms the emitter by self-alignment.

摘要翻译： PCT No.PCT / JP85 / 00432 Sec。 371日期：1986年4月9日 102（e）日期1986年4月9日PCT提交1985年7月31日PCT公布。 第WO86 / 01338号公报 日期：1986年2月27日。本发明涉及一种制造半导体器件的方法，该半导体器件适于形成具有较低产量波动特性的双极晶体管，其产率高。 根据本发明，通过从多晶硅膜13掺杂杂质形成移植物基底（或非本征基底）20，同时通过光刻技术形成发射体。 由于发射极是通过光刻技术形成的，因此在掩模取向时发射极的形成位置不可避免地会发生变化，但是它对晶体管特性的影响可以忽略不计。 因此，与通过自对准形成发射极的方法相比，可以形成具有更均匀特性的双极晶体管。

公开(公告)号：US4926235A

公开(公告)日：1990-05-15

申请号：US106861

申请日：1987-10-13

申请人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

发明人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

IPC分类号： H01L21/285 ,  H01L21/763 ,  H01L29/423

CPC分类号： H01L21/763 ,  H01L21/28525 ,  H01L29/42304

摘要： A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

摘要翻译： 公开了一种半导体器件，其包括双极晶体管，每个双极晶体管具有形成在半导体衬底的每个突出部分内的发射极，基极和集电极以及用于器件隔离的沟槽。 双极晶体管和沟槽彼此隔开预定间隔。 根据这种布置，基极接触的宽度变得均匀，并且可以有效地防止晶体管特性的任何变化。