公开(公告)号：US6147588A

公开(公告)日：2000-11-14

申请号：US271605

申请日：1999-03-17

申请人： Akinori Nakayama ,  Ryouichi Urahara ,  Yukio Sakabe

发明人： Akinori Nakayama ,  Ryouichi Urahara ,  Yukio Sakabe

IPC分类号： H01C7/10 ,  H01C7/112 ,  H01C7/18 ,  H01C7/13

CPC分类号： H01C7/18 ,  H01C7/112

摘要： The present invention provides a varistor which has low variation in electric characteristics and enhanced withstand electrostatic voltage and which can be fired at low temperature; as well as a method for producing the same. The laminated varistor comprises a sintered laminate formed by laminating alternating layers of semiconducting ceramic which comprises ZnO as a primary component and at least Bi oxide as a secondary component, and internal electrodes which predominantly comprise Pt and Pd as an inevitable impurity; and external electrodes maintaining electrical contact with the internal electrodes, wherein the Pd content is controlled to be about 0.1 wt. % or less based on the content of Pt, which is a primary component of the internal electrodes.

摘要翻译： 本发明提供一种变阻器，其电特性变化小，抗静电电压提高，可在低温下烧制; 以及其制造方法。 层叠压敏电阻器包括通过将包含ZnO作为主要成分的交替层和至少Bi氧化物作为次要组分层叠的交替层和主要包含Pt和Pd作为不可避免的杂质的内部电极而形成的烧结层叠体。 以及与内部电极保持电接触的外部电极，其中Pd含量被控制在约0.1wt。 基于作为内部电极的主要成分的Pt的含量的％以下。

公开(公告)号：US6090735A

公开(公告)日：2000-07-18

申请号：US167895

申请日：1998-10-07

申请人： Akinori Nakayama ,  Terunobu Ishikawa ,  Hideaki Nimi ,  Ryouichi Urahara ,  Yukio Sakabe

发明人： Akinori Nakayama ,  Terunobu Ishikawa ,  Hideaki Nimi ,  Ryouichi Urahara ,  Yukio Sakabe

IPC分类号： C04B35/01 ,  C04B35/50 ,  H01B1/08 ,  H01C7/04 ,  H01C17/065

CPC分类号： C04B35/01 ,  C04B35/50 ,  H01B1/08 ,  H01C17/06533 ,  H01C7/043 ,  H01C7/045 ,  C04B2235/3217 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3256 ,  C04B2235/3258 ,  C04B2235/3262 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3277 ,  C04B2235/3293 ,  C04B2235/3294 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/446 ,  C04B2235/447 ,  C04B2235/96

摘要： A semiconductive ceramic composition having negative resistance-temperature characteristics, wherein the composition comprises lanthanum cobalt oxide as the primary component, and, as secondary components, at least one oxide of an element selected from B, Fe and Al and at least one oxide of an element selected from Si, Zr, Hf, Ta, Sn, Sb, W, Mo, Te, Ce, Nb, Mn, Th and P. A semiconductive ceramic composition having a resistivity of approximately 10 .OMEGA..multidot.cm to 100 .OMEGA..multidot.cm at room temperature is obtained by controlling the amount of additives. Since the resistivity at room temperature can be enhanced to several times or more that of the conventional compositions while characteristics of the conventional compositions are maintained, the composition may be widely applied to control heavy current.

摘要翻译： 一种具有负电阻 - 温度特性的半导体陶瓷组合物，其中所述组合物包含氧化镧钴作为主要组分，并且作为次要组分，选自B，Fe和Al中的至少一种元素的氧化物和至少一种氧化物 选自Si，Zr，Hf，Ta，Sn，Sb，W，Mo，Te，Ce，Nb，Mn，Th和P中的一种元素。在室温下电阻率为约10欧米伽至100欧米伽x厘米的半导体陶瓷组合物 通过控制添加剂的量获得。 由于在保持常规组合物的特性的同时，常规组合物的电阻率可以提高到常规组合物的几倍或更多，因此组合物可广泛用于控制大电流。

公开(公告)号：US06472339B2

公开(公告)日：2002-10-29

申请号：US09157062

申请日：1998-09-18

申请人： Mitsutoshi Kawamoto ,  Hideaki Niimi ,  Ryouichi Urahara ,  Yukio Sakabe

发明人： Mitsutoshi Kawamoto ,  Hideaki Niimi ,  Ryouichi Urahara ,  Yukio Sakabe

IPC分类号： C04B35468

CPC分类号： B82Y30/00 ,  C01G23/006 ,  C01P2002/50 ,  C01P2002/76 ,  C01P2002/77 ,  C01P2004/62 ,  C01P2004/64 ,  C04B35/4682

摘要： The present invention provides barium titanate semiconductive ceramic having low specific resistance at room temperature and high withstand voltage, which fully satisfies the demand for enhancing withstand voltage. The average ceramic grain size of the barium titanate semiconductive ceramic is controlled to about 0.9 &mgr;m or less. By this control, the ceramic possesses low specific resistance at room temperature and high withstand voltage fully satisfying a recent demand for enhancing withstand voltage and may suitably used for applications such as controlling temperature and limiting current, or in exothermic devices for constant temperature. Accordingly, the barium titanate semiconductive ceramic enables an apparatus using the same to have enhanced performance and reduced size.

摘要翻译： 本发明提供了在室温下具有低电阻率和高耐压的钛酸钡半导体陶瓷，其完全满足提高耐电压的要求。 钛酸钡半导体陶瓷的平均陶瓷粒径控制在0.9μm以下。 通过该控制，陶瓷在室温下具有低的电阻率和高耐受电压，完全满足了近来对提高耐受电压的要求，并且可以适用于诸如控制温度和限制电流的应用，或用于恒温的放热装置中。 因此，钛酸钡半导体陶瓷使得能够使用其的装置具有增强的性能和减小的尺寸。

公开(公告)号：US5703000A

公开(公告)日：1997-12-30

申请号：US796916

申请日：1997-02-06

申请人： Akinori Nakayama ,  Terunobi Ishikawa ,  Hiroshi Takagi ,  Yukio Sakabe

发明人： Akinori Nakayama ,  Terunobi Ishikawa ,  Hiroshi Takagi ,  Yukio Sakabe

IPC分类号： C04B35/00 ,  H01C7/04 ,  C04B35/50

CPC分类号： H01C7/043

摘要： Provided is a semiconductive ceramic composition comprising a lanthanum cobalt oxide and having a negative resistance-temperature characteristic, which contains, as the side component, a chromium oxide in an amount of from about 0.005 to 30 mol % in terms of chromium, and also a semiconductive ceramic device comprising the composition. The device is usable for rush current inhibition, for motor start-up retardation and for halogen lamp protection, and is also usable in temperature-compensated crystal oscillators.

摘要翻译： 本发明提供一种包含氧化镧钴并具有负电阻温度特性的半导体陶瓷组合物，其含有以铬计为0.005〜30摩尔％左右的铬氧化物作为副成分， 包含该组合物的半导体陶瓷装置。 该装置可用于冲击电流抑制，电机启动延迟和卤素灯保护，也可用于温度补偿晶体振荡器。

公开(公告)号：US5324986A

公开(公告)日：1994-06-28

申请号：US901750

申请日：1992-06-22

申请人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

发明人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

IPC分类号： H01C7/10 ,  H01C7/112 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15

CPC分类号： H01C7/10 ,  H01C7/112

摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.

摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。

公开(公告)号：US5119062A

公开(公告)日：1992-06-02

申请号：US615369

申请日：1990-11-19

申请人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

发明人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

IPC分类号： H01C7/10

CPC分类号： H01C7/10

摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.

摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。

公开(公告)号：US06780456B2

公开(公告)日：2004-08-24

申请号：US10315949

申请日：2002-12-11

申请人： Tatsuo Kunishi ,  Toshi Numata ,  Junichi Saitoh ,  Yukio Sakabe

发明人： Tatsuo Kunishi ,  Toshi Numata ,  Junichi Saitoh ,  Yukio Sakabe

IPC分类号： B05D512

CPC分类号： H05K3/244 ,  C23C18/1607 ,  C23C18/1651 ,  C23C18/1669 ,  C23C18/34 ,  C23C18/36 ,  C23C18/44 ,  C23C18/54

摘要： A work piece is mixed with Ni pieces having an average diameter of 1 mm and exhibiting catalytic activity to oxidation reaction of sodium phosphinate (NaH2PO2) added as a reducing agent in a plating bath containing the reducing agent and a Ni salt to form a Ni—P film on an electrode made of Cu, Ag or Ag—Pd by auto-catalytic electroless plating. Then, the work piece is dipped in a plating bath containing an Au salt to form an Au film on the surface of the Ni—P film by substitutional electroless plating. This method is capable of forming a desired plating film only on a desired portion at a low cost.

摘要翻译： 将工件与平均直径为1mm的Ni片混合，并且在含有还原剂的镀浴和Ni盐中显示出对作为还原剂加入的次膦酸钠（NaH 2 PO 2）的氧化反应的催化活性，形成Ni- 通过自动催化无电镀法在Cu，Ag或Ag-Pd制成的电极上的P膜。 然后，将工件浸入含有Au盐的镀浴中，通过替代无电镀在Ni-P膜的表面上形成Au膜。 该方法能够以低成本仅在期望的部分形成期望的镀膜。

公开(公告)号：US5672220A

公开(公告)日：1997-09-30

申请号：US636685

申请日：1996-04-23

申请人： Nagato Omori ,  Yukio Hamaji ,  Yoshiaki Mori ,  Yukio Sakabe

发明人： Nagato Omori ,  Yukio Hamaji ,  Yoshiaki Mori ,  Yukio Sakabe

IPC分类号： H01G4/12 ,  H01G4/30 ,  H05K1/03 ,  H05K3/46 ,  C04B37/00

CPC分类号： H01G4/30 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629

摘要： A plurality of dielectric ceramic sheets having inner electrodes thereon are laminated and sintered. The ceramic sheets are made of a non-reducing dielectric material, and the inner electrodes are made of a base metal or a base metal alloy. After a binder removing step, the laminate is sintered in a mixed gas which contains either one or both of carbon dioxide with a purity of 99.9% or more and carbon monoxide with a purity of 99.9% or more as its main constituent and further contains hydrogen and oxygen with their densities regulated.

摘要翻译： 其上具有内电极的多个介电陶瓷片被层压并烧结。 陶瓷片由非还原电介质材料制成，内电极由贱金属或贱金属合金制成。 在粘合剂除去步骤之后，将层压体在含有纯度为99.9％以上的二氧化碳中的一种或两种作为主要成分的纯度为99.9％以上的一氧化碳的混合气体中烧结，并且还含有氢 氧气密度调节。

公开(公告)号：US5328718A

公开(公告)日：1994-07-12

申请号：US969027

申请日：1992-10-30

申请人： Yoshio Abe ,  Yukio Hamaji ,  Yukio Sakabe

发明人： Yoshio Abe ,  Yukio Hamaji ,  Yukio Sakabe

IPC分类号： C01G23/00 ,  C04B35/46 ,  C04B35/468 ,  H01B3/00 ,  H01B3/12 ,  H01L21/314 ,  H01L21/316 ,  B05D5/12

CPC分类号： H01L21/31691 ,  H01L41/1871 ,  H01L41/317

摘要： A thin film of barium titanate is formed on a substrate by immersing the substrate in an aqueous solution containing barium ions and titanium alkoxide. The aqueous solution may contain not more than 20 vol % of one or more alkanolamines expressed by the general formula:HO(C.sub.n H.sub.2n)mNH.sub.3-mwhere n is not more than 10, and m=1, 2 or 3.

摘要翻译： 通过将基板浸入含有钡离子和钛醇盐的水溶液中，在基板上形成钛酸钡薄膜。 水溶液可以含有不多于20体积％的一种或多种由以下通式表示的链烷醇胺：HO（CnH2n）mNH3-m，其中n不大于10，m = 1,2或3。

公开(公告)号：US5146313A

公开(公告)日：1992-09-08

申请号：US395343

申请日：1989-08-17

申请人： Takeyuki Kato ,  Yasunobu Yoneda ,  Yukio Sakabe

发明人： Takeyuki Kato ,  Yasunobu Yoneda ,  Yukio Sakabe

IPC分类号： C04B41/90 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC分类号： H05K3/38 ,  H01L23/49811 ,  H01L23/49866 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2924/15312 ,  Y10T428/12458 ,  Y10T428/12528 ,  Y10T428/12576 ,  Y10T428/1284

摘要： A metallized ceramic structure includes a ceramic substrate preferably aluminum nitride and a metallic layer preferably tungsten bonded to the ceramic substrate. First and second mixture layers are formed between the ceramic substrate and the metallic layer to bond the ceramic substrate and the metallic layer. The first mixture layer is in contact with the ceramic substrate and the second mixture layer is in contact with the metallic layer. Each of the mixture layers includes a mixture of ceramic of the ceramic substrate and the metal of the metallic layer. The second mixture layer has a lower percentage of the ceramic than the first mixture layer.

摘要翻译： 金属化陶瓷结构包括优选氮化铝的陶瓷衬底和优选钨结合到陶瓷衬底的金属层。 在陶瓷基板和金属层之间形成第一和第二混合层，以结合陶瓷基板和金属层。 第一混合物层与陶瓷基片接触，第二混合物层与金属层接触。 每个混合层包括陶瓷衬底的陶瓷和金属层的金属的混合物。 第二混合物层具有比第一混合物层低百分比的陶瓷。