公开(公告)号：US20180164870A1

公开(公告)日：2018-06-14

申请号：US15372838

申请日：2016-12-08

申请人： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

发明人： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296

摘要： A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US20180336111A1

公开(公告)日：2018-11-22

申请号：US15599587

申请日：2017-05-19

申请人： Alexander Gendler ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Michael Mishaeli ,  Ilya Zegelman ,  Krishnakanth V. Sistla

发明人： Alexander Gendler ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Michael Mishaeli ,  Ilya Zegelman ,  Krishnakanth V. Sistla

IPC分类号： G06F11/22 ,  G06F1/32 ,  G06F13/16 ,  G06F11/27

CPC分类号： G06F11/2284 ,  G06F1/3287 ,  G06F1/3296 ,  G06F11/2236 ,  G06F11/27 ,  G06F11/321 ,  G06F13/1663

摘要： In one embodiment, a processor includes a core and a power controller coupled to the core that in turn includes a self-test control circuit. The self-test circuit is adapted to: isolate the core during field operation; cause the core to execute at least one diagnostic test at a first operating voltage to identify a guard band voltage for the core; and cause the core to enter into a low power state after the execution of the at least one diagnostic test. Other embodiments are described and claimed.

公开(公告)号：US20140115351A1

公开(公告)日：2014-04-24

申请号：US14143939

申请日：2013-12-30

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

摘要： In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于当前时间间隔确定多域处理器的功率预算的方法，确定要分配给处理器的第一和第二域的功率预算的一部分，以及控制频率 基于所分配的部分的域。 这样的确定和分配可以在处理器的运行期间动态地执行。 描述和要求保护其他实施例。

公开(公告)号：US08707060B2

公开(公告)日：2014-04-22

申请号：US12263431

申请日：2008-10-31

申请人： Efraim Rotem ,  Doron Rajwan ,  Lev Finkelstein

发明人： Efraim Rotem ,  Doron Rajwan ,  Lev Finkelstein

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/206 ,  Y02D10/16

摘要： Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed.

摘要翻译： 描述与处理器的动态热响应的确定性管理有关的方法和装置。 在一个实施例中，可用的热余量可用于以确定性方式提取性能潜力，例如使其减少甚至消除产品与产品的变化。 还公开并要求保护其他实施例。

公开(公告)号：US20130173941A1

公开(公告)日：2013-07-04

申请号：US13780087

申请日：2013-02-28

申请人： Avinash N. Ananthakrishnan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

发明人： Avinash N. Ananthakrishnan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/16

摘要： In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在多域处理器的控制器中确定多域处理器的第二域的温度是否大于节流阀阈值和跨域之和的方法 余量，如果是，则将多域处理器的第一域的频率降低所选择的量。 以这种方式，由于域的热耦合，可以允许第二域的温度降低。 描述和要求保护其他实施例。

公开(公告)号：US20130111120A1

公开(公告)日：2013-05-02

申请号：US13282896

申请日：2011-10-27

申请人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F9/54

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。

公开(公告)号：US20100115304A1

公开(公告)日：2010-05-06

申请号：US12263421

申请日：2008-10-31

申请人： Lev Finkelstein ,  Efraim Rotem ,  Aviad Cohen ,  Ronny Ronen ,  Doron Rajwan

发明人： Lev Finkelstein ,  Efraim Rotem ,  Aviad Cohen ,  Ronny Ronen ,  Doron Rajwan

IPC分类号： G06F1/32 ,  G06F1/00

CPC分类号： G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.

摘要翻译： 描述与多个处理器核心的电源管理相关的方法和装置。 在一个实施例中，本地可以利用一个或多个技术（例如，基于每个核心）来管理处理器中的功率消耗。 在另一个实施例中，功率可以基于能量考虑而分布在处理器的不同功率层之间。 还公开并要求保护其他实施例。

公开(公告)号：US20050259682A1

公开(公告)日：2005-11-24

申请号：US10182753

申请日：2001-02-02

申请人： Yuval Yosef ,  Haim Neerman ,  Doron Rajwan ,  Edan Ayal

发明人： Yuval Yosef ,  Haim Neerman ,  Doron Rajwan ,  Edan Ayal

IPC分类号： H04J3/16 ,  H04L12/18 ,  H04L29/08

CPC分类号： H04L12/1859 ,  H04L12/18 ,  H04L67/2823 ,  H04L67/2828 ,  H04L67/2842

摘要： A method of emulating an interactive connection, comprising: generating a request for interactive data from an interactive server, at a client; intercepting said request by an agent; responsive to said request, retrieving at least some of said data from a continuous retransmission of said data, by said agent; and displaying said data including said retrieved data at said client.

摘要翻译： 一种模拟交互式连接的方法，包括：在客户端处产生来自交互式服务器的交互式数据的请求; 由代理人截取该请求; 响应于所述请求，由所述代理从所述数据的连续重传中检索所述数据中的至少一些; 以及在所述客户端显示包括所述检索的数据的所述数据。

公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.