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    Self-balanced silicon-controlled rectification device
    1.
    发明授权
    Self-balanced silicon-controlled rectification device 有权

    公开(公告)号：US09748219B1

    公开(公告)日：2017-08-29

    申请号：US15241365

    申请日：2016-08-19

    Applicant: AMAZING MICROELECTRONIC CORP.

    Inventor： Ming-Dou Ker ,  Woei-Lin Wu ,  James Jeng-Jie Peng ,  Ryan Hsin-Chin Jiang

    IPC: H01L27/02 ,  H01L23/528

    CPC classification number: H01L27/0262 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/87

    Abstract: A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

    Three-dimension (3D) integrated circuit (IC) package
    2.
    发明授权
    Three-dimension (3D) integrated circuit (IC) package 有权
    三维（3D）集成电路（IC）封装

    公开(公告)号：US09224702B2

    公开(公告)日：2015-12-29

    申请号：US14104251

    申请日：2013-12-12

    Applicant: AMAZING MICROELECTRONIC CORP.

    Inventor： Ming-Dou Ker ,  Che-Hao Chuang

    IPC: H01L21/00 ,  H01L23/60 ,  H01L23/00

    CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16227

    Abstract: A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.

    Abstract translation: 公开了一种三维（3D）集成电路（IC）封装。 3D IC封装具有具有表面的封装衬底。 具有或不抑制瞬态电压的至少一个集成电路（IC）芯片和至少一个瞬态电压抑制器（TVS）芯片布置在基板的表面上并彼此电连接。 IC芯片独立于TVS芯片。 彼此堆叠的IC芯片和TVS芯片布置在封装基板上。 或者，IC芯片和TVS芯片一起排列在形成在封装基板上的插入件上。

    Method for fabricating a planar micro-tube discharger structure
    3.
    发明授权
    Method for fabricating a planar micro-tube discharger structure 有权
    平面微管放电器结构的制造方法

    公开(公告)号：US09024516B2

    公开(公告)日：2015-05-05

    申请号：US14109297

    申请日：2013-12-17

    Applicant: Amazing Microelectronic Corp.

    Inventor： Tung-Yang Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

    IPC: H01J1/88 ,  H01J19/42 ,  H01K1/18 ,  H02H9/00 ,  H01H47/00 ,  H05F3/00 ,  H01J9/02 ,  H01J17/06

    CPC classification number: H01J9/02 ,  H01J17/066

    Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

    Abstract translation: 提供一种制造基于半导体的平面微管放电器结构的方法，包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块，在图案上形成绝缘层 电极和分离块，并将绝缘层填充到间隙中。 形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径，该结构具有非常高的可靠性和可再利用性。

    Active surge protection structure and surge-to-digital converter thereof
    4.
    发明授权
    Active surge protection structure and surge-to-digital converter thereof 有权

    公开(公告)号：US10700517B2

    公开(公告)日：2020-06-30

    申请号：US16042144

    申请日：2018-07-23

    Applicant: AMAZING MICROELECTRONIC CORP.

    Inventor： Wen-Chieh Chen ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

    IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00

    Abstract: An active surge protection structure is provided between a power line and a core circuit, comprising a surge-to-digital converter and a clamp circuit. The surge-to-digital converter comprises a plurality of surge detection circuit. Each surge detection circuit detects a surge event occurring on the power line and generates a digital signal. The clamp circuit is disposed adjacent to the core circuit and electrically connected with the surge-to-digital converter and the power line where the core circuit is connected for dissipating surge energy. The clamp circuit receives and is driven by the digital signals from the surge-to-digital converter such that its protection flexibility can be achieved according to the digital signals. By employing the present invention, it is extraordinarily advantageous of improving system stability and achieving comprehensive surge protection with configuration of driving capability dependent on surge levels.

    Test method for eliminating electrostatic charges
    5.
    发明授权
    Test method for eliminating electrostatic charges 有权

    公开(公告)号：US10041995B2

    公开(公告)日：2018-08-07

    申请号：US14597413

    申请日：2015-01-15

    Applicant: AMAZING MICROELECTRONIC CORP.

    Inventor： Ming-Dou Ker ,  Che-Hao Chuang

    IPC: G01R31/20 ,  H01L23/495 ,  G01R31/28

    CPC classification number: G01R31/2893 ,  H01L2224/49171

    Abstract: In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.

    Bipolar transistor device
    6.
    发明授权
    Bipolar transistor device 有权

    公开(公告)号：US09728530B1

    公开(公告)日：2017-08-08

    申请号：US15384736

    申请日：2016-12-20

    Applicant: AMAZING MICROELECTRONIC CORP.

    Inventor： Ming-Dou Ker ,  Woei-Lin Wu ,  James Jeng-Jie Peng ,  Ryan Hsin-Chin Jiang

    IPC: H01L27/102 ,  H01L27/02 ,  H01L29/732 ,  H01L27/082 ,  H01L29/36

    CPC classification number: H01L27/0259 ,  H01L27/0826 ,  H01L29/36 ,  H01L29/732

    Abstract: A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

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