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公开(公告)号：US11961797B2
公开(公告)日：2024-04-16
申请号：US17468981
申请日：2021-09-08
发明人： Keun Soo Kim , Jae Yun Kim , Byoung Jun Ahn , Dong Soo Ryu , Dae Byoung Kang , Chel Woo Park
IPC分类号： H01L23/498 , H01L23/31 , H01L23/42 , H01L23/433 , H01L25/10 , H01L23/538
CPC分类号： H01L23/49894 , H01L23/3121 , H01L23/42 , H01L23/433 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L25/105 , H01L23/5389 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/3511 , H01L2224/48091 , H01L2924/00014 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00
摘要： A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
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公开(公告)号：US11495505B2
公开(公告)日：2022-11-08
申请号：US17018434
申请日：2020-09-11
发明人： Gyu Wan Han , Won Bae Bang , Ju Hyung Lee , Min Hwa Chang , Dong Joo Park , Jin Young Khim , Jae Yun Kim , Se Hwan Hong , Seung Jae Yu , Shaun Bowers , Gi Tae Lim , Byoung Woo Cho , Myung Jea Choi , Seul Bee Lee , Sang Goo Kang , Kyung Rok Park
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/13 , H01L21/56 , H01L23/00 , H01L25/065 , H01L23/31 , H01L25/18 , H01L23/498
摘要： In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
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公开(公告)号：US20240258182A1
公开(公告)日：2024-08-01
申请号：US18633941
申请日：2024-04-12
发明人： Gyu Wan Han , Won Bae Bang , Ju Hyung Lee , Min Hwa Chang , Dong Joo Park , Jin Young Khim , Jae Yun Kim , Se Hwan Hong , Seung Jae Yu , Shaun Bowers , Gi Tae Lim , Byoung Woo Cho , Myung Jea Choi , Seul Bee Lee , Sang Goo Kang , Kyung Rok Park
IPC分类号： H01L23/13 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/18
CPC分类号： H01L23/13 , H01L21/568 , H01L23/3185 , H01L23/49816 , H01L24/48 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/48145 , H01L2224/48157 , H01L2224/85005 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要： In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
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公开(公告)号：US11961775B2
公开(公告)日：2024-04-16
申请号：US17982713
申请日：2022-11-08
发明人： Gyu Wan Han , Won Bae Bang , Ju Hyung Lee , Min Hwa Chang , Dong Joo Park , Jin Young Khim , Jae Yun Kim , Se Hwan Hong , Seung Jae Yu , Shaun Bowers , Gi Tae Lim , Byoung Woo Cho , Myung Jea Choi , Seul Bee Lee , Sang Goo Kang , Kyung Rok Park
IPC分类号： H01L23/48 , H01L21/56 , H01L23/00 , H01L23/13 , H01L23/31 , H01L23/498 , H01L23/52 , H01L25/065 , H01L25/18 , H01L29/40
CPC分类号： H01L23/13 , H01L21/568 , H01L23/3185 , H01L23/49816 , H01L24/48 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/48145 , H01L2224/48157 , H01L2224/85005 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要： In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
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公开(公告)号：US11749654B2
公开(公告)日：2023-09-05
申请号：US17521750
申请日：2021-11-08
发明人： Gi Tae Lim , Jae Yun Kim , Myung Jea Choi
IPC分类号： H01L23/538 , H01L25/10 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/56 , H01L21/52
CPC分类号： H01L25/105 , H01L21/52 , H01L21/56 , H01L23/3128 , H01L23/49822 , H01L23/49838 , H01L23/5386 , H01L24/16 , H01L24/48 , H01L2224/16227 , H01L2224/48227 , H01L2225/1058
摘要： In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.
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公开(公告)号：US20220415769A1
公开(公告)日：2022-12-29
申请号：US17897556
申请日：2022-08-29
发明人： Jae Yun Kim , Gi Tae Lim , Woon Kab Jung , Ju Hoon Yoon , Dong Joo Park , Byong Woo Cho , Gyu Wan Han , Ji Young Chung , Jin Seong Kim , Do Hyun Na
IPC分类号： H01L23/498 , H01L23/31 , H01L21/50 , H01L23/00 , H01L23/538
摘要： A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.
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公开(公告)号：US20220352129A1
公开(公告)日：2022-11-03
申请号：US17864891
申请日：2022-07-14
发明人： Gi Tae Lim , Jae Yun Kim , Myung Jae Choi , Min Hwa Chang , Mi Kyoung Choi
IPC分类号： H01L25/10 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/56 , H01L23/538 , H01L21/52
摘要： In one example, a semiconductor structure comprises a frontside substrate comprising a conductive structure, a backside substrate comprising a base substrate and a cavity substrate contacting the base substrate, wherein the backside substrate is over a top side of the frontside substrate and has a cavity and an internal interconnect contacting the frontside substrate, and a first electronic component over the top side of the frontside substrate and in the cavity. The first electronic component is coupled with the conductive structure, and an encapsulant is in the cavity and on the top side of the frontside substrate, contacting a lateral side of the first electronic component, a lateral side of the cavity, and a lateral side of the internal interconnect. Other examples and related methods are also disclosed herein.
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公开(公告)号：US20240347442A1
公开(公告)日：2024-10-17
申请号：US18634621
申请日：2024-04-12
发明人： Keun Soo Kim , Jae Yun Kim , Byoung Jun Ahn , Dong Soo Ryu , Dae Byoung Kang , Chel Woo Park
IPC分类号： H01L23/498 , H01L23/31 , H01L23/42 , H01L23/433 , H01L23/538 , H01L25/10
CPC分类号： H01L23/49894 , H01L23/3121 , H01L23/42 , H01L23/433 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L25/105 , H01L23/5389 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/3511
摘要： A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
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公开(公告)号：US12107035B2
公开(公告)日：2024-10-01
申请号：US17897556
申请日：2022-08-29
发明人： Jae Yun Kim , Gi Tae Lim , Woon Kab Jung , Ju Hoon Yoon , Dong Joo Park , Byong Woo Cho , Gyu Wan Han , Ji Young Chung , Jin Seong Kim , Do Hyun Na
IPC分类号： H01L23/498 , H01L21/50 , H01L23/00 , H01L23/31 , H01L23/538
CPC分类号： H01L23/49811 , H01L21/50 , H01L23/3128 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L24/92 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/16227 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73253 , H01L2224/81815 , H01L2224/83191 , H01L2224/83203 , H01L2224/8321 , H01L2224/92225 , H01L2224/92242 , H01L2924/181 , H01L2924/18161 , H01L2224/81815 , H01L2924/00014 , H01L2224/8321 , H01L2924/00014 , H01L2224/83203 , H01L2924/00014 , H01L2224/2929 , H01L2924/0665 , H01L2224/2919 , H01L2924/0665 , H01L2224/293 , H01L2924/00014 , H01L2224/92242 , H01L2224/81 , H01L2924/181 , H01L2924/00 , H01L2224/131 , H01L2924/014 , H01L2224/1329 , H01L2924/00014 , H01L2224/133 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.
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公开(公告)号：US20240203803A1
公开(公告)日：2024-06-20
申请号：US18082012
申请日：2022-12-15
发明人： Jae Yun Kim
IPC分类号： H01L23/053 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L23/053 , H01L21/4817 , H01L21/4853 , H01L21/563 , H01L23/3185 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2924/15311 , H01L2924/18161 , H01L2924/19105
摘要： In one example, an electronic device comprises a substrate comprising a top side, a bottom side, a lateral side, and a conductive structure, a first electronic component over the top side of the substrate and coupled with the conductive structure, an encapsulant contacting the top side of the substrate, the bottom side of the substrate, and the lateral side of the substrate, a lid over the first electronic component and over the encapsulant, and a second electronic component over the top side of the substrate and coupled with the conductive structure, wherein the second electronic component is between the first electronic component and the lateral side of the substrate. Other examples and related methods are also disclosed herein.
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