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280 条记录 (耗时 0.025 秒)

    SOI low capacitance body contact
    1.
    发明授权
    SOI low capacitance body contact 失效
    SOI低电容体接触

    公开(公告)号：US06368903B1

    公开(公告)日：2002-04-09

    申请号：US09527858

    申请日：2000-03-17

    申请人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

    发明人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

    IPC分类号： H01L2100

    CPC分类号： H01L29/66757 ,  H01L29/78615

    摘要： An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

    摘要翻译： 一种FET器件及其制造方法，包括：第一介电层; 介电层上的基底层; 形成在基板层中的第一导电类型的沟道区; 在沟道区上形成在衬底层上方的栅极; 在衬底层中形成的第二导电类型的FET扩散区，每个具有边缘的扩散区，FET扩散区的边缘被沟道区分隔; 以及从所述沟道区域连续延伸的所述第一导电类型的体接触区域。 体接触区域中的第一导电类型材料比沟道区域中的第一导电类型材料薄。 FET还包括形成在身体接触区域上的第二电介质层。

    SOI low capacitance body contact
    2.
    发明授权
    SOI low capacitance body contact 失效

    公开(公告)号：US06624475B2

    公开(公告)日：2003-09-23

    申请号：US09996413

    申请日：2001-11-29

    申请人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

    发明人： Andres Bryant ,  Randy W. Mann ,  Anthony K. Stamper

    IPC分类号： H01L2701

    CPC分类号： H01L29/66757 ,  H01L29/78615

    摘要： An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

    Method of forming damascene filament wires
    4.
    发明授权
    Method of forming damascene filament wires 有权
    形成镶嵌长丝丝的方法

    公开(公告)号：US07915162B2

    公开(公告)日：2011-03-29

    申请号：US11839767

    申请日：2007-08-16

    申请人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey P. Gambino ,  Anthony K. Stamper

    发明人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey P. Gambino ,  Anthony K. Stamper

    IPC分类号： H01L21/44

    CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.

    摘要翻译： 一种形成半导体器件的方法。 第一电介质层沉积在衬底上并与衬底直接机械接触。 第一硬掩模沉积在第一介电层上。 第一和第二沟槽形成在第一介电层和第一硬掩模内。 第二沟槽比第一沟槽宽。 第一保形衬垫沉积在第一硬掩模之上并且在第一和第二沟槽内，其一部分被去除，留下第一保形衬垫的剩余部分与衬底，第一介电层和 第一个硬面罩，而不是在第一个硬面罩。 铜沉积在第一保形衬垫上以过满填充第一和第二沟槽，并被平坦化以除去其过量以形成铜的平坦表面。

    Low-cost FEOL for ultra-low power, near sub-vth device structures
    8.
    发明授权
    Low-cost FEOL for ultra-low power, near sub-vth device structures 有权
    低成本的FEOL用于超低功耗，靠近次级装置结构

    公开(公告)号：US07816738B2

    公开(公告)日：2010-10-19

    申请号：US11164651

    申请日：2005-11-30

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

    摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。