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    Sidewall spacers for CMOS circuit stress relief/isolation and method for making
    2.
    发明授权
    Sidewall spacers for CMOS circuit stress relief/isolation and method for making 失效
    用于CMOS电路应力释放/隔离的侧壁间隔件和制造方法

    公开(公告)号：US4729006A

    公开(公告)日：1988-03-01

    申请号：US840180

    申请日：1986-03-17

    申请人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

    发明人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/34 ,  H01L29/78

    CPC分类号： H01L21/76224

    摘要： A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

    摘要翻译： 一种用于在用于制造CMOS集成电路的半导体上形成完全凹陷（平面）隔离区域的方法，所得到的半导体结构包括在其中形成有台面的P掺杂硅衬底中，形成接触的硼硅酸盐玻璃的低粘度侧壁间隔物 其中所述台面的侧壁被指定为在其中形成有N沟道器件; 然后用TEOS填充与台面相邻的基板中的沟槽; 并加热该结构直到侧壁间隔物中的硼扩散到指定台面的侧壁中以形成通道停止点。 这些侧壁间隔件通过减轻TEOS中的内部机械应力来减少TEOS中的裂纹的发生，并允许通过扩散形成通道停止，从而允许台面壁基本上垂直。

    Self-aligned lateral bipolar transistors
    4.
    发明授权
    Self-aligned lateral bipolar transistors 失效
    自对准侧向双极晶体管

    公开(公告)号：US4641170A

    公开(公告)日：1987-02-03

    申请号：US762669

    申请日：1985-08-05

    申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/72

    CPC分类号： H01L29/6625 ,  H01L29/66272 ,  H01L29/66606

    摘要： An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical ohmic contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes electrical contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An electrical ohmic contact is made to the centrally located base region which contact is separated from the vertical conductive layers by the second insulating layer.

    摘要翻译： 描述了包括小面积横向双极的集成电路结构及其制造方法。 提供了半导体本体，例如单晶硅晶片，其表面区域通过介电隔离图案与其它这样的区域隔离。 至少两个窄宽度PN结区域位于至少一个表面区域内。 每个PN结的宽度尺寸基本上是其电接触点。 基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。 具有相反电导率的基极PN结基区位于发射极和集电极结之间并且与发射极和集电极结邻接。 基本上水平的导电层与每个垂直导电层的边缘电接触，并通过第一电绝缘层与表面区域分离。 第二绝缘层覆盖保形导电层。 将水平导电层图案化成具有彼此分离的导电线。 第三电绝缘层位于图案化的水平导电层上。 通过第三电绝缘层中的开口对每个水平导电层进行电欧姆接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域电接触。 对中心位置的基极区域进行电欧姆接触，该接触部分通过第二绝缘层与垂直导电层分离。

    Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
    5.
    发明授权
    Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer 失效
    防止亚微米范围侧壁图像传输线路的不对称蚀刻的方法

    公开(公告)号：US4648937A

    公开(公告)日：1987-03-10

    申请号：US792931

    申请日：1985-10-30

    申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Ronald N. Schulz

    发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Ronald N. Schulz

    IPC分类号： G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22

    CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/31116 ,  Y10S438/945 ,  Y10S438/951

    摘要： In the process of sidewall image transfer, a vertical step is etched in some material and then a conformal layer of some other material is deposited over the step. By reactive ion etching the conformal material can be anisotropically etched which results in a sidewall spacer of the second material on the vertical surfaces of the step material. By removing the step material, the free standing spacer can then be used as a mask. One area in which improvement is desired is in the selectivity of the etch of the spacer to the material immediately below it. Because of the limited number of materials and reactive ion etching gases it is difficult to avoid an etch in the underlying layer as the sidewall spacer is formed. A suitable etch stop is employed beneath the step material to avoid the problem. Because of the usual technology, the spacer material is plasma deposited silicon nitride and the step material is photoresist. Polysilicon, aluminum or similar metal is employed as an etch stop, since it is not by a CF.sub.4 based gas which is used to form the spacer.

    摘要翻译： 在侧壁图像转印的过程中，在一些材料中蚀刻垂直台阶，然后在该台阶上沉积一些其它材料的共形层。 通过反应离子蚀刻，共形材料可被各向异性地蚀刻，这导致第二材料的侧壁间隔物在台阶材料的垂直表面上。 通过除去台阶材料，可以将自立式间隔物用作掩模。 需要改进的一个领域是间隔物的蚀刻对其正下方的材料的选择性。 由于材料数量和反应离子蚀刻气体的数量有限，所以当形成侧壁间隔物时难以避免下层蚀刻。 在步骤材料之下采用合适的蚀刻停止件以避免该问题。 由于通常的技术，间隔材料是等离子体沉积氮化硅，步骤材料是光致抗蚀剂。 使用多晶硅，铝或类似金属作为蚀刻阻挡层，因为它不是通过用于形成间隔物的基于CF 4的气体。

    Method for making self-aligned lateral bipolar transistors
    6.
    发明授权
    Method for making self-aligned lateral bipolar transistors 失效
    制造自对准侧向双极晶体管的方法

    公开(公告)号：US4551906A

    公开(公告)日：1985-11-12

    申请号：US560629

    申请日：1983-12-12

    申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/265 ,  H01L21/225

    CPC分类号： H01L29/6625 ,  H01L29/66272 ,  H01L29/66606

    摘要： A semiconductor body having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An ohmic contact is made to the base region which is separated from the vertical conductive layers by the second insulating layer.

    摘要翻译： 提供了具有通过介电隔离图案与其它这样的区域隔离的表面区域的半导体本体。 至少两个窄宽度PN结区域位于至少一个表面区域内。 每个PN结的宽度尺寸基本上是其电接触点。 基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。 具有相反电导率的基极PN结区域位于发射极和集电极结之间并且邻近发射极和集电极结。 基本上水平的导电层与每个垂直导电层的边缘电接触并且通过第一电绝缘层与表面区域分离。 第二绝缘层覆盖保形导电层。 将水平导电层图案化成具有彼此分离的导电线。 第三电绝缘层位于图案化的水平导电层上。 通过第三电绝缘层中的开口对每个水平导电层进行电接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域接触。 与通过第二绝缘层与垂直导电层分离的基极区域进行欧姆接触。

    Fabrication methods for high performance lateral bipolar transistors
    7.
    发明授权
    Fabrication methods for high performance lateral bipolar transistors 失效
    高性能横向双极晶体管的制造方法

    公开(公告)号：US4583106A

    公开(公告)日：1986-04-15

    申请号：US754698

    申请日：1985-07-15

    申请人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

    发明人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

    IPC分类号： H01L21/331 ,  H01L21/60 ,  H01L21/74 ,  H01L21/8224 ,  H01L29/735 ,  H01L29/72

    CPC分类号： H01L21/76897 ,  H01L21/743 ,  H01L21/8224 ,  H01L29/6625 ,  H01L29/735

    摘要： The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

    摘要翻译： 描述了具有其基极宽度和晶体管的发射极区域最小化的横向晶体管。 横向晶体管元件的这种最小化给出了高性能。 通常可以是PNP晶体管的横向晶体管形成在体内具有掩埋的N +区域的单晶半导体本体。 P型发射体区域位于体内。 N型基极区域位于发射极区域的侧边周围。 P型集电极区域位于围绕基极区域周边的主体中。 作为发射极区域的发射极接触点的第一P +多晶硅层与发射极区物理和电接触，并充当其电接触。 第二个P +多晶硅层位于主体的表面上，以与收集器区域物理和电接触。 在第二多晶硅层的边缘上的垂直绝缘体层将两个多晶硅层彼此隔离。 其表面的N基区位于垂直绝缘体层的宽度的下方。 从主体的表面延伸到掩埋的N +区域的N +到达区域用作通过N +区域层到基极区域的电接触。 垂直绝缘体的宽度具有等于横向PNP晶体管的期望基极宽度以及横向PNP的集电极和发射极结的横向扩散的宽度。 优选的结构是使发射体形成在通道或沟槽周边周围，该通道或沟槽在其底部具有诸如二氧化硅之类的绝缘层。 寄生晶体管几乎完全被这种掩埋氧化物隔离所消除。

    Fabrication process of sub-micrometer channel length MOSFETs
    8.
    发明授权
    Fabrication process of sub-micrometer channel length MOSFETs 失效
    亚微米通道长度MOSFET的制造工艺

    公开(公告)号：US4419809A

    公开(公告)日：1983-12-13

    申请号：US335893

    申请日：1981-12-30

    申请人： Jacob Riseman ,  Paul J. Tsang

    发明人： Jacob Riseman ,  Paul J. Tsang

    IPC分类号： H01L27/088 ,  H01L21/033 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/66659 ,  H01L21/0337 ,  H01L21/2815 ,  H01L29/78 ,  Y10S438/942 ,  Y10S438/947

    摘要： Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

    摘要翻译： 其中描述了一种半导体集成电路的制造方法，该半导体集成电路具有亚微米栅极长度场效应晶体管器件，其中在将半导体区域彼此隔离的半导体衬底中形成表面隔离图案。 这些半导体区域中的某些被指定为包含场效应晶体管器件。 在隔离图案表面上形成可以被指定为场效应晶体管器件的栅极介电层的一部分的绝缘层。 然后在其上形成第一多晶硅层。 然后在第一多晶层上形成诸如二氧化硅，氮化硅等的掩模层。 蚀刻该结构以产生具有基本垂直侧壁的图案化的第一多晶硅层，其中一些侧壁延伸穿过某些器件区域。 在这些垂直侧壁上形成受控亚微米厚度导电层。 然后去除图案层，其留下亚微米厚度的导电侧壁层的图案部分延伸穿过特定的器件区域。 侧壁导电层用作场效应晶体管器件的栅电极。 然后完成离子注入以形成用于器件区域中的场效应器件的期望的源极/漏极元件。 导电层和所得到的栅电极可以由多晶硅金属硅化物或多晶硅化物（多晶硅和金属硅化物的组合）组成。

    Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition
    9.
    发明授权
    Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition 失效
    使用反应离子蚀刻和多晶沉积制造单电极U-MOSFET随机存取存储器的方法

    公开(公告)号：US4252579A

    公开(公告)日：1981-02-24

    申请号：US36722

    申请日：1979-05-07

    申请人： Irving T. Ho ,  Jacob Riseman

    发明人： Irving T. Ho ,  Jacob Riseman

    IPC分类号： H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/31 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/20 ,  H01L21/302

    CPC分类号： H01L27/10864 ,  G11C11/35 ,  G11C11/404 ,  H01L21/76229 ,  H01L27/10841 ,  H01L29/7827 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/131

    摘要： A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

    摘要翻译： 一种用于制造高密度，介电隔离的U形MOSFET的方法。 在优选的方法中，提供了其上具有N +层的单晶硅P衬底，N +层上的P层和P层上的N +层。 通过反应离子蚀刻技术，在体内通过P基板形成U形开口的图案。 这种开口图案填充有诸如二氧化硅的绝缘体材料。 N +掺杂多晶硅的导电层沉积在该硅体的裸露表面上。 在二氧化硅填充的开口上的多晶硅中形成开口。 然后通过例如在多晶硅层上的热氧化来生长二氧化硅层。 反向离子蚀刻用于通过P衬底上的层并且进入P衬底中产生基本上U形的开口，以将单晶硅的区域基本上二等分。 该蚀刻步骤在单晶硅区域中形成两个存储单元，并且在多晶硅层中形成每列单元格的位线。 通过在合适的环境中的热氧化，在U形开口的单晶硅表面上生长二氧化硅栅极绝缘体。 导电掺杂的多晶硅沉积在二氧化硅栅极绝缘体层上的U形开口中，直到开口被填充并覆盖该体的表面。 以合适的图案蚀刻身体表面上的导电掺杂多晶硅，以产生随机存取存储器件的字线。